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| author | Tim Newsome <tim@sifive.com> | 2016-09-01 13:17:56 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-09-01 16:35:15 -0700 |
| commit | 55d31b6f933bda107a399fdd169bd01a7ea5da6c (patch) | |
| tree | f6a1407be80f25c9b33e3e8d93d7cc2a663a633b | |
| parent | 83e90dd49da860c4af50325dec13355abe5386bb (diff) | |
| download | riscv-tests-55d31b6f933bda107a399fdd169bd01a7ea5da6c.zip riscv-tests-55d31b6f933bda107a399fdd169bd01a7ea5da6c.tar.gz riscv-tests-55d31b6f933bda107a399fdd169bd01a7ea5da6c.tar.bz2 | |
Add some immediate trigger tests.
| -rwxr-xr-x | debug/gdbserver.py | 17 | ||||
| -rw-r--r-- | debug/programs/trigger.S | 12 |
2 files changed, 23 insertions, 6 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 2aa589a..851644b 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -393,6 +393,14 @@ class TriggerTest(DeleteServer): self.assertIn("Breakpoint", output) self.assertIn("_exit", output) + def test_execute_immediate(self): + """Test an execute breakpoint on the first instruction executed out of + debug mode.""" + main = self.gdb.p("$pc") + self.gdb.command("hbreak *0x%x" % (main + 4)) + self.gdb.c() + self.assertEqual(self.gdb.p("$pc"), main+4) + def test_load_address(self): self.gdb.command("rwatch *((&data)+1)"); output = self.gdb.c() @@ -401,6 +409,15 @@ class TriggerTest(DeleteServer): self.gdb.p("(&data)+1")) self.exit() + def test_load_address_immediate(self): + """Test a load address breakpoint on the first instruction executed out + of debug mode.""" + write_loop = self.gdb.p("&write_loop") + self.gdb.command("rwatch data"); + self.gdb.c() + self.assertEqual(self.gdb.p("$pc"), write_loop) + self.assertEqual(self.gdb.p("$a0"), self.gdb.p("(&data)+1")) + def test_store_address(self): self.gdb.command("watch *((&data)+3)"); output = self.gdb.c() diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index e5dfa67..25d2b89 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -3,11 +3,11 @@ #undef MCONTROL_TYPE #undef MCONTROL_DMODE #ifdef __riscv64 -# define MCONTROL_TYPE (0xfU<<((64)-4)) -# define MCONTROL_DMODE (1U<<((64)-5)) +# define MCONTROL_TYPE (0xf<<(64-4)) +# define MCONTROL_DMODE (1<<(64-5)) #else -# define MCONTROL_TYPE (0xfU<<((32)-4)) -# define MCONTROL_DMODE (1U<<((32)-5)) +# define MCONTROL_TYPE (0xf<<(32-4)) +# define MCONTROL_DMODE (1<<(32-5)) #endif .global main @@ -25,10 +25,10 @@ read_loop: blt t0, t2, read_loop la a0, data - li t0, 0 + li t0, 1 write_loop: - addi t0, t0, 1 sw t0, 0(a0) + addi t0, t0, 1 addi a0, a0, 4 blt t0, t2, write_loop |