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authorMegan Wachs <megan@sifive.com>2018-09-04 12:49:06 -0700
committerMegan Wachs <megan@sifive.com>2018-09-04 12:49:06 -0700
commitaec52a0d04677447a7eaa8bc41d3caed897335e3 (patch)
treec605b08fbd5ae68ce860b9da517b6141ac31ec48
parent4dddbc79ada7f0a836cf538676c57c8df103ccf6 (diff)
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debug: Add first cut to call compliance testscompliance_tests
-rwxr-xr-xdebug/gdbserver.py26
1 files changed, 26 insertions, 0 deletions
diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index c362e1d..2ef91bc 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -1015,6 +1015,32 @@ class PrivRw(PrivTest):
if privilege in self.supported:
assertEqual(actual, privilege)
+class ComplianceTest(GdbTest):
+
+ def test(self):
+ output = self.gdb.command("monitor riscv test_compliance")
+ #TODO: Fix OpenOCD to remove the -rtos riscv requirement
+ assert(("ALL TESTS PASSED") in output or ("Please run with -rtos riscv to run compliance test.") in output)
+
+ def compile(self):
+ pass
+
+class SystemBusAccessConfigRegTest(GdbTest):
+
+ def test(self):
+ result = self.gdb.command("monitor riscv dmi_read 0x38")
+ if (int(result, base=16) == 0):
+ return 'not_applicable'
+
+ self.gdb.command("monitor riscv set_prefer_sba on")
+ command = "monitor riscv test_sba_config_reg 0x%08x %d 0x%08x off" % (
+ self.target.harts[0].ram, # base address to target
+ min(self.target.harts[0].ram_size, 100), # size to target
+ self.target.harts[0].ram - 4) # Illegal region to target
+ print command
+ output = self.gdb.command(command)
+ assert("ALL TESTS PASSED") in output
+
# XXX temporarily disabling this test
#class PrivChange(PrivTest):
# def test(self):