riscv-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
ceasetest2	Check basic debugging still works in CeaseMulti	Tim Newsome	20 months
debug	Add debug statement.	Tim Newsome	4 years
debug_disassemble	debug: On failure, disassemble close instructions.	Tim Newsome	21 months
disable_unavailable	debug: Disable Unavailable tests.	Tim Newsome	8 months
master	README: add link to toolchain (#569)	Daniel Maslowski	14 days
misc	Make newer version of pylint happy.	Tim Newsome	5 years
python3	Move to Python 3.	Tim Newsome	5 years
riscv-tests-sail	removed the env/ directory, which was a submodule dir. replaced at a higher l...	William McSpaddden	7 weeks
tmp	tmp	Andrew Waterman	5 years
trigger_priority	Remove ineffective tests.	Tim Newsome	2 years
[...]


Age	Commit message	Author	Files	Lines
2016-09-04	Add support for a "--with-xlen" argumentrvt-master	Palmer Dabbelt	6	-6/+35
2016-03-01	Negative float -> unsigned int conversions return 0	Andrew Waterman	1	-17/+17
2016-02-29	Merge pull request #8 from riscv/sqrt-171	Colin Schmidt	1	-0/+5
2016-02-29	remove comments now that tests passsqrt-171	Colin Schmidt	1	-2/+0
2016-02-28	Fix capitalization of XLEN variable	Andrew Waterman	1	-1/+1
2016-02-28	Strip big-endian tests	Andrew Waterman	4	-24/+0
2016-02-27	Merge pull request #10 from riscv/travis-dev	Palmer Dabbelt	5	-103/+302
2016-02-27	only build the rv32 bit tests if xlen is 32	Colin Schmidt	1	-0/+3
2016-02-27	remove malloc declaration from dhrystone	Colin Schmidt	1	-1/+0
2016-02-27	allow make variables to be overwritten update configure	Colin Schmidt	4	-102/+299
[...]