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| author | Andrew Waterman <andrew@sifive.com> | 2017-02-15 15:20:06 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-02-15 15:26:04 -0800 |
| commit | 4678e84c040531a48eff2108fd9212660bf527ae (patch) | |
| tree | 293343a64c9017bf71add2dfe657a49c18c9cfd7 /machine/vm.h | |
| parent | 6667bc4c42fd9968527644e32841757234285efd (diff) | |
| download | riscv-pk-4678e84c040531a48eff2108fd9212660bf527ae.zip riscv-pk-4678e84c040531a48eff2108fd9212660bf527ae.tar.gz riscv-pk-4678e84c040531a48eff2108fd9212660bf527ae.tar.bz2 | |
Incorporate sptbr/sfence.vma changes
Diffstat (limited to 'machine/vm.h')
| -rw-r--r-- | machine/vm.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/machine/vm.h b/machine/vm.h index 4e6bcc1..6d3da4e 100644 --- a/machine/vm.h +++ b/machine/vm.h @@ -6,11 +6,11 @@ #define MEGAPAGE_SIZE ((uintptr_t)(RISCV_PGSIZE << RISCV_PGLEVEL_BITS)) #if __riscv_xlen == 64 -# define VM_CHOICE VM_SV39 +# define SPTBR_MODE INSERT_FIELD(0, SPTBR64_MODE, SPTBR_MODE_SV39) # define VA_BITS 39 # define GIGAPAGE_SIZE (MEGAPAGE_SIZE << RISCV_PGLEVEL_BITS) #else -# define VM_CHOICE VM_SV32 +# define SPTBR_MODE INSERT_FIELD(0, SPTBR32_MODE, SPTBR_MODE_SV32) # define VA_BITS 32 #endif @@ -19,7 +19,7 @@ extern pte_t* root_page_table; static inline void flush_tlb() { - asm volatile("sfence.vm"); + asm volatile ("sfence.vma"); } static inline pte_t pte_create(uintptr_t ppn, int type) |