aboutsummaryrefslogtreecommitdiff
path: root/tcl
AgeCommit message (Collapse)AuthorFilesLines
2023-07-08jtag/stlink: add STLINK-V3PWR supportLaurent LEMELE2-2/+2
STLINK-V3PWR is both a standalone debugger probe compatible with STLINK-V3 and a source measurement unit (SMU). Link: http://www.st.com/stlink-v3pwr This code adds support for the debugger probe functionality. Change-Id: Ib056e55722528f922c5574bb6fbf77e2f2b2b0c1 Signed-off-by: Laurent LEMELE <laurent.lemele@st.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7755 Tested-by: jenkins
2023-07-08ipdbg/pld: ipdbg can get tap and hub/ir from pld driver.Daniel Anselmi2-2/+2
To start a ipdbg server one needs to know the tap and the instruction code to reach the IPDBG-Hub. This instruction is vendor/family specific. Knowledge which can be provided by the pld driver. Change-Id: I13eeb9fee895d65cd48544da4704fcc9b528b869 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7369 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-08pld/virtex2: add program/refresh commandDaniel Anselmi4-0/+5
Change-Id: If6d237a6f27c4232849f73d08e7ca74276e6d464 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7714 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08tcl/cpld: add config files for more xilinx fpga familiesDaniel Anselmi9-1/+194
Use configurable virtex pld driver to add support for more xilinx fpga families. Change-Id: Iff10c8c511787734fa289bdba15f03131d51e071 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7352 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-07-08pld: give devices a name for referencing in scriptsDaniel Anselmi17-17/+17
Change-Id: I05e8596ffacdb6cd8da4dd8a40bb460183f4930a Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7728 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-07-08tcl/board/bemicro: source cycloneiii.cfg from correct pathDaniel Anselmi1-1/+1
Change-Id: Ib1d1be1067107633949a202a05f7fd06831ba84b Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7751 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-06-10target/ti-cjtag: make switching to JTAG more reliableLorenz Brun1-0/+1
The current cJTAG to JTAG switching commands for TI chips are not particularly reliable, especially on chips with accurate timing. On a Raspberry Pi the existing sequence has (depending on cabling and chip) a ~50% chance of working, on a much better-behaved FT2232H it doesn't manage to enable full JTAG at all. This change runs a bunch of test-idle cycles before actually attempting to switch to full JTAG. This makes the switch reliable even at high clock speeds (>100kHz) and from precise sources like the FT2232H. Change-Id: I9293e884bf3e9606d529756ae4483b844d3c39db Reported-by: Phil Wiggum <p1mail2015@mail.com> Fixes: https://sourceforge.net/p/openocd/tickets/375/ Signed-off-by: Lorenz Brun <lorenz@brun.one> Reviewed-on: https://review.openocd.org/c/openocd/+/7419 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-06-10flash/nor: add support for NXP QN908xiosabi1-0/+38
This patch adds support for the NXP QN908x family of Bluetooth microcontrollers, such as the QN9080. This chip features a Cortex-M4F with 512 KiB of flash on all the available versions, although the documentation suggests that there might be 256 kB versions as well. The initial support allows to read, erase and write the whole user flash area. Three new sub-commands under the new "qn908x" command are added in this patch as well: disable_wdog to disabled the watchdog, mass_erase to perform a mass erase and allow_brick to allow programming images that disable the SWD interface. Disabling the watchdog is required after a "reset halt" in order to run the CRC algorithm from RAM when verifying the chip. However, this is not done automatically on probing or other initialization since disabling the watchdog might interfere with debugging real applications. The "mass_erase" command allows to erase the whole flash without probing it, since in some scenarios the chip can be locked such that no flash or ram can be accessed from the SWD interface, allowing only to run a mass_erase to be able to flash the program. The flashing process allows to compute a checksum, similar to the lpc2000 driver "calc_checksum" but done over a different region of the memory. This checksum is required to be present for the QN908x bootloader ROM to boot, and otherwise is useless. As with the lpc2000 design, verification when using "calc_checksum" is expected to fail if the checksum was not valid in the image being verified. This was manually tested on a QN9080, including the scan-view, AddressSanitizer/UBSan and test coverage configurations. Change-Id: Ibd6d8f3608654294795085fcaaffb448b77cc58b Co-developed-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de> Signed-off-by: iosabi <iosabi@protonmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5584 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-06-02jtag/vdebug: adding xtensa configJacek Wuwer3-27/+194
This change adds the extensa sample target and board configurations. it removes the obsoleted vd_xtensa_jtag.cfg from targets. Change-Id: I9d4d25abde46c0b15e5211a973012447872cb405 Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7723 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-06-02tcl/board/calao-usb-a9g20-c01: add proper initializationWolfram Sang1-0/+158
Initialize clocks to max speed and setup SDRAM. NAND support is still incomplete. Originally found at: elinux.org/index.php?title=Calao_Atmel_AT91_development_board&oldid=73933 Updated the code from 2011 and improved it a bit. Signed-off-by: Wolfram Sang <wsa@kernel.org> Change-Id: I83474e07c8de8cc3b5d058029551935549693ef9 Reviewed-on: https://review.openocd.org/c/openocd/+/7578 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-06-02Add/Correct STM8L15xx2/3/4/6/8 devicesDominik Wernberger7-2/+170
Change-Id: I83fe1e50821ec15e1853aca96ebb32fe1ff5328f Signed-off-by: Dominik Wernberger <dominik.wernberger@gmx.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7690 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-05-27flash/jtagspi: sending command and setting parameters without probing.Daniel Anselmi1-1/+11
Change-Id: I6b9d90265ca5112b9ab2aae97bb4c6cf3ebc4112 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7432 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2023-05-24flash/stm32l4x: support STM32C0x devicesTarek BOCHKATI1-0/+74
this new STM32 series family introduces 2 devices: STM32C011xx (0x443) and STM32C031xx (0x453) both devices have 32 Kbytes single flash bank. Change-Id: I4e890789e44e3b174c0e9c0e1068383ecdbb865f Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6874 Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-05-18tcl/target: Add support for TMS570LC43xxPhil Kirkpatrick2-9/+9
Added support for TMS570LC43xx series parts. This uses the pre-existing ti_tms570.cfg parent config. In ti_tms570.cfg, dbgbase was changed. Note 1: Based on the following TI E2E post, the previous dbgbase was wrong and the new value isn't due to a difference in parts. Link: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1106954/tms570ls3137-debugging-with-openocd Note 2: Both the previous dbgbase and the one suggested in the TI E2E post have the 2 LSB set. In the current version of OpenOCD, this will cause cortex_a_read_cpu_memory_fast and cortex_a_write_cpu_memory_fast to fail due to an alignment checks in mem_ap_<read/write>_buf_noincr()->mem_ap_<read/write>(). In all other uses of dbgbase for arm cortex parts, the 2 LSB are masked and ignored. Change-Id: Ic936722e5a4cfc7161b0df1fe3325ee12fd901c6 Signed-off-by: Phil Kirkpatrick <p.kirkpatrick@reflexaerospace.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7682 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30pld: add support for cologne chip gatemate fpgasDaniel Anselmi2-0/+32
Change-Id: I0bf5a52ee6a7f0287524619114eba0cfccf6ac81 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7565 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30pld: add support for gowin devicesDaniel Anselmi2-0/+48
Change-Id: Idd1a09514bbbbe0a7b54d69010f6c2f91215fd1d Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7368 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30pld: add support for altera/intel devicesDaniel Anselmi13-49/+304
Change-Id: I7977d39c9037ae71139f78c8d381f5f925dc3489 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7355 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30pld: add support for efinix devicesDaniel Anselmi3-0/+64
Change-Id: Ie520e761c255ba1335d5aab9c6825f160a6151d9 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7288 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-04-30pld: add support for lattice certus devicesDaniel Anselmi3-0/+50
Change-Id: Ic50a724e5793000fca11f35ba848c2d317c3cbab Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7398 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-30pld: add support for lattice ecp5 devicesDaniel Anselmi2-0/+21
Change-Id: Ib2f0933da3abe7429abca86d6aaa50ad85ce72c7 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7397 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-04-30pld: add support for lattice ecp2 and ecp3 devicesDaniel Anselmi2-0/+53
Change-Id: I29c227c37be464f7ecc97a30d9cf3da1442e2b7f Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7396 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-04-30tcl/target: renesas gen3 Set target to armv8r for Cortex-R52Julien Massot1-8/+13
Cortex-R52 is an ARMv8-R processor supporting only AArch32 Profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh> Change-Id: I663ae4bf1d3026d7c9e4c5950a79e7ddf1bd6564 Reviewed-on: https://review.openocd.org/c/openocd/+/6805 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-14tcl: cpld/xilinx-xc7: remove virtex-7 devices with ir-length > 6Daniel Anselmi1-8/+10
They have an ir length of 22, 24 or 38 bit and different command codes. Change-Id: I488e8613f1c4d017e1590111f60b2725ec62964b Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7387 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-04-14tcl: zynq_7000: add missing id codesDaniel Anselmi1-4/+20
Add missing ID codes and ignore the version in the ID. Change-Id: Idd2d3a5eddb6995f3af1c45afd2adf76ce3442bf Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7386 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-03-28tcl/board: add Calao USB-A9G20Wolfram Sang1-0/+14
Add a basic config. Signed-off-by: Wolfram Sang <wsa@kernel.org> Change-Id: Ie68e5fbb26b1c2f3028e561af0255fa71ec61828 Reviewed-on: https://review.openocd.org/c/openocd/+/7524 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-03-28tcl/board/calao-usb-a9260: fix and refactor broken supportWolfram Sang4-60/+14
The old configuration files did not work because of a missing 'at91sam9260minimal.cfg' file. Also, the config files were placed wrongly. Update them, put them to the proper location, merge the two supported boards into one, remove now superfluous include, remove defunct web page, etc.. Tested with a Calao USB-A9G20 and a hacked 'device_desc' to match. Native support for it will come next. Signed-off-by: Wolfram Sang <wsa@kernel.org> Change-Id: Iec578c8777c5a6134e132dbac17c2988c7634742 Reviewed-on: https://review.openocd.org/c/openocd/+/7522 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-03-18tcl: remove exec permission to tcl config filesAntonio Borneo2-0/+0
With the new checkpatch we will not get this type of issues anymore. In mean time, let's fix what we have missed during the review process. Change-Id: Iecebf9d43f51a29ee09505d360792793afd24b40 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: 53556fcded05 ("tcl/interface: add Ashling Opella-LD FTDI config files") Reviewed-on: https://review.openocd.org/c/openocd/+/7530 Tested-by: jenkins
2023-03-18tcl/tools/test_cpu_speed: Fix register nameMarc Schink1-1/+1
Use correct register name after it has beed changed in commit 11ee500bffe4 ("target/armv7m: Rename xPSR to xpsr") Change-Id: I3648848f4b47af2d20d60c3e0ecef78f75f6d605 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/7473 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-03-18tcl/board/at91sam9g20-ek: remove outdated FIXMEWolfram Sang1-4/+0
It was fixed by e94180571 ("at91sam9: factorise cpu support") in 2011. Signed-off-by: Wolfram Sang <wsa@kernel.org> Change-Id: I95ea149b45a9902424bf9068b4a2830c17ddc6be Reviewed-on: https://review.openocd.org/c/openocd/+/7525 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2023-03-03tlc/interface: does fix source of raspberrypi-gpio-connector.cfgTomas Deingruber1-1/+1
in raspberrypi-native.cfg Fixes: bec6c0eb094f (tcl/interface: universal config for all Raspberry Pi models) Signed-off-by: Tomas Deingruber <Deingruber.Tomas@gmail.com> Change-Id: I632c8acd84974937849b5fdf2943239def17bd6d Reviewed-on: https://review.openocd.org/c/openocd/+/7512 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-28tcl/target: add rescue mode to RP2040 configTomas Vanek1-0/+30
Integrate a rescue mode inspired by [1]. The current OpenOCD must be restarted before normal work with the RP2040 because the rescue debug port must not be activated (or the target is reset every 'dap init'). To continue without restarting OpenOCD we would need to switch off the configured rescue dap. Change-Id: Ia05b960f06747063550c166e461939d92e232830 Link: [1] https://github.com/raspberrypi/openocd/blob/rp2040/tcl/target/rp2040-rescue.cfg Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7327 Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2023-01-28tcl/interface: universal config for all Raspberry Pi modelsTomas Vanek3-73/+104
Speed calibration coeffs are computed from cpufreq/scaling_max_freq and from the device-tree compatibility information. Raspberry Pi linux offers /dev/gpiomem for non-root access to the GPIO registers since ~2016. Do not configure 'bcm2835gpio peripheral_base' as it is necessary only if /dev/mem is used - it requires running OpenOCD as root - it's a security risk so it should be avoided. The configuration of the GPIO connector (40-pin header) is factored out and ready to use in interface configuration for other driver (e.g. linux gpiod). Mark raspberrypi2-native.cfg as deprecated and redirect it to raspberrypi-native.cfg Change-Id: Icce856fb660b45374e94174da279feb51f529908 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7264 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-21stm32f3x: Allow overriding the flash bank sizeAndreas Fritiofson1-1/+9
Same mechanism as in stm32f1x.cfg reused here. Change-Id: I81f02feb2b655e8259341b22180f3a8b82e28d05 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7438 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15tcl/target: enable -rtos hwthreadAntonio Borneo4-8/+4
The rtos hwthread has been merged in 2019 with commit 85ba2dc4c6ab ("rtos/hwthread: add hardware-thread pseudo rtos"). During review in patchset 19 the name of the rtos has been changed from 'hawt' to 'hwthread'. Some target config file was already merged ready for hwthread, but keeping the relevant lines commented and still reporting the old name. Enable rtos hwtread to the target that were supposed to use it. Fix the name of the rtos. Change-Id: I877862dcdba39f26462bb542bac06d1a5f5f222d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7384 Tested-by: jenkins
2023-01-15tcl: add a configuration file for Nuvoton M541 & NUC442/472 seriesZale Yu1-0/+62
This patch is picked from the tcl part of OpenOCD-Nuvoton's commit ("flash: supported Nuvoton M4 series. jtag: Used HW reset instead of auto reset. tcl: added a configuration file for Nuvoton M4 series.") [1] to support the communication with Nuvoton's Cortex-M4 chips: M541 & NUC442/472 series. This patch has been tested with Nuvoton's NuTiny-SDK-NUC472 development board [2]. The code comes from the commit basically. Jian-Hong Pan tweaked for the compatibility with current OpenOCD. So, leave the author as Zale Yu. [1]: https://github.com/OpenNuvoton/OpenOCD-Nuvoton/commit/c2d5b8bfc705 [2]: https://www.nuvoton.com/export/resource-files/UM_NuTiny-SDK- NUC472_EN_Rev1.02.pdf Signed-off-by: Zale Yu <cyyu@nuvoton.com> Signed-off-by: Jian-Hong Pan <chienhung.pan@gmail.com> Change-Id: I27ac58dd1c98a76e791a4f1117c31060cf5522e8 Reviewed-on: https://review.openocd.org/c/openocd/+/7330 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15tcl/target: remove rp2040-core0.cfgTomas Vanek1-52/+0
rp2040-core0.cfg configuration file was intended for a special adapter which selects a SWD multidrop target on its own. This means that rp2040-core0.cfg is totally unusable with a standard SWD adapter. The file was marked as deprecated in 0.12 release. The reworked rp2040.cfg can be restricted to use just one core: openocd ... -c 'set USE_CORE 0' -f target/rp2040.cfg Remove the obsoleted config. Change-Id: Id886471622bb4a8cb83f5c4c3660657407aaaf74 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7326 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15tcl/target: add SMP mode to rp2040.cfgTomas Vanek1-3/+9
Add the variable selected configuration for SMP debug with rtos hwthread. Use SMP by default. Change-Id: I1c37d91688a3ab58d65c15686737892965711adc Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7242 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15flash/nor/avrf: add ATmega32U4 supportKyle Schwarz1-0/+30
Add new chip info and tcl target Change-Id: Ib9d33d1b145a8659857b7a6cc9c5acba047f41d1 Signed-off-by: Kyle Schwarz <zeranoe@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7081 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2023-01-15nds32: drop it, together with aice adapter driverAntonio Borneo5-60/+0
The target nds32 and its companion adapter aice have not received any real improvement since 2013. It has been hard to keep them aligned during the evolution of OpenOCD code, with no way for maintainers to really check if they are still working. No real documentation is present for them in OpenOCD. The nds32 code triggers ~50 errors/warnings with scan-build. The arch nds32 has been dropped from Linux kernel v5.18-rc1. For all the reasons above, this code has been deprecated with commit 2e5df83de7f2 ("nds32: deprecate it, together with aice adapter driver") and tagged to be dropped before v0.13.0. Let it r.i.p. in OpenOCD git history. While there, drop from checkpatch list the camelcase symbols that where only used in this code. Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7382 Tested-by: jenkins
2022-11-28tcl: max326xx: fix target scripts for latest version of OpenOCDRocco Marco Guglielmi3-3/+9
Change-Id: Iec5aba3a082f2e25f21d7ca173ed710894b370a4 Signed-off-by: Rocco Marco Guglielmi <roccomarco.guglielmi@gmail.com> Change-Id: Ia83850e326661c8acb0712a280fdf961258322a4 Reviewed-on: https://review.openocd.org/c/openocd/+/7373 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-11-15tcl/interface: fix raspberrypi2-native.cfg speed coefficientTomas Vanek1-2/+2
The speed coefficient for Raspberry Pi 2 was probably calibrated for a scaled down clock frequency. To prevent JTAG/SWD overclocking, use the value corresponding to the 'official' maximum CPU clock. Change-Id: Iaff58b092198dce6d6552c9d31d6a3ba4aaaa2d5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7305 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-11-11tcl/cpld/xilinx-xcu: fix typoGeorge Voicu1-1/+1
Fix typo in comments Signed-off-by: George Voicu <razvanvg@hotmail.com> Change-Id: Icc2d770e73f896e20dd347de324328030544bdb9 Reviewed-on: https://review.openocd.org/c/openocd/+/7333 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-21tcl/target: add basic RP2040 target configTomas Vanek2-0/+86
The existing rp2040-core0.cfg configuration file was intended for a special adapter which selects a SWD multidrop target on its own. This means that rp2040-core0.cfg is totally unusable with a standard SWD adapter. To fix the problem, mark rp2040-core0.cfg as deprecated and add rp2040.cfg, a basic config file with multidrop target selection. Change-Id: I5194e42f529a2d9645481424b7c66ab61efa44ee Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7275 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-21tcl/stm32l5x|u5x: support HLA adapters in non-secure mode onlyTarek BOCHKATI1-5/+12
instrument "target/stm32x5x_common.cfg" used by both STM32L5x/U5x to support HLA adapters like "interface/stlink.cfg" in non-secure mode if the device switches to secure mode, the debug session will be stopped immediately (with an explanatory message). Change-Id: I645fdd55e3448ef82d0ddcc396f42fd7b2f39ac3 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reported-by: Patrik Bachan <diggit@users.sourceforge.net> Fixes: https://sourceforge.net/p/openocd/tickets/317/ Reviewed-on: https://review.openocd.org/c/openocd/+/6546 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins
2022-10-15tcl/xtensa: some fixes at xtensa-core-esp32s3.cfgErhan Kurubas1-84/+63
Some config changes required to run ESP32-S3 with full feature set Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I38022bb5ff5830e1cf9d11d6fe795ea99d91e9db Reviewed-on: https://review.openocd.org/c/openocd/+/7254 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15tcl/xtensa: some fixes at xtensa-core-esp32s2.cfgErhan Kurubas1-37/+37
Some config changes required to run ESP32-S2 with full feature set Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ie0a742442254ec6e95d4e05be40213b079a94dab Reviewed-on: https://review.openocd.org/c/openocd/+/7253 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-15tcl/xtensa: some fixes at xtensa-core-esp32.cfgErhan Kurubas1-39/+3
Some config changes required to run ESP32 with full feature set Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: I484324f8497ec7934bb73164c638fc5f6460fcc4 Reviewed-on: https://review.openocd.org/c/openocd/+/7252 Tested-by: jenkins Reviewed-by: Ian Thompson <ianst@cadence.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-10-12tcl/target: fix rp2040-core0.cfg work area backup.Tomas Vanek1-1/+4
The work area should be backed up. The flash probe runs an algorithm on the target CPU. The flash is probed during gdb connect if gdb_memory_map is enabled (is enabled by default). Without backup the target memory gets corrupted on gdb connect. Change-Id: I3344b9dc6cbf904d49f3b05ab104b541d1d63422 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7257 Tested-by: jenkins Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
2022-10-08tcl/target/ti_k3: Handle swd vs jtagNishanth Menon1-1/+4
Since all the device definition when accessing device from jtag is also valid when accessing from swd, lets make sure the configuration can handle the same. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I5af071137fd8c3b52cc4ef72401f8eba952f9cad Reviewed-on: https://review.openocd.org/c/openocd/+/7090 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-09-23target/stm32l5x,stm32u5x: fix trace settingsTomas Vanek1-3/+4
The STM32L5 and U5 devices have DBGMCU_CR trace related bits changed wrt other STM32 devices. Fix the setting in configuration script. Change-Id: I0bbc48e7b1290b603c6966cf5ddd42df389e6ede Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/7117 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
generated by cgit v1.1 at 2024-10-12 11:55:45 +0000