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2022-09-19Add Digilent JTAG-HS2 cJTAG configurationmrv961-0/+19
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-06-06tcl: add Espressif riscv targets (ESP32-C2 & ESP32-C3) (#706)Erhan Kurubas5-0/+282
Change-Id: I48fead33f5fd5890a7724cd5f500f2d14e2a5ffa Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-05-03Merge branch 'master' into from_upstreamTim Newsome3-22/+51
Conflicts: tcl/target/gd32vf103.cfg I kept our version, except I changed the flash device as happened in mainline. Once this file settles down in mainline, we can copy it wholesale into this fork. Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
2022-04-24tcl/target/gd32vf103: add flash bankTomas Vanek1-1/+15
The flash is compatible with stm32f1x, reuse the driver. Extend the size of work area to RAM size of the smallest device. Stop watchdogs before flash programming. Change-Id: I67a7654a6e196f9d4b2409edaa7990c53334437e Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6711 Tested-by: jenkins Reviewed-by: Tim Newsome <tim@sifive.com>
2022-04-23tcl/target/stm32l4x: align format/order/comments with stm32f4xMarkus Reiter1-11/+14
Change-Id: Ie97bb2f56b582bc735c238af5f160fcb28a61eb0 Signed-off-by: Markus Reiter <me@reitermark.us> Reviewed-on: https://review.openocd.org/c/openocd/+/6933 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-23tcl/target/stm32l4x: switch to new TPIU/SWO supportMarkus Reiter1-7/+33
Change-Id: I3362fa7292eae7a3ba119cf6183f8bc4cbd5cbd4 Signed-off-by: Markus Reiter <me@reitermark.us> Reviewed-on: https://review.openocd.org/c/openocd/+/6932 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-23tcl/target/stm32l4x: set default WORKAREASIZE to smallest deviceMarkus Reiter1-2/+2
Change-Id: Ia8bfb664ff28bd0579492032ce513b010e71c593 Signed-off-by: Markus Reiter <me@reitermark.us> Reviewed-on: https://review.openocd.org/c/openocd/+/6931 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-04-23tcl/target/stm32f4x: fix nameMarkus Reiter1-1/+1
Change-Id: I9baa79d8cf402991e6638c255a91728b8a77020c Signed-off-by: Markus Reiter <me@reitermark.us> Reviewed-on: https://review.openocd.org/c/openocd/+/6930 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-04-11Merge branch 'master' into from_upstreamTim Newsome30-529/+578
Conflicts: src/server/server.c src/target/breakpoints.c src/target/semihosting_common.c src/target/target.c Change-Id: I48bd3608c688c69d8aac0667fc46e2de5466a9f1
2022-04-03tcl/board: Add NXP FRDM-K64FMarc Schink1-0/+15
Change-Id: I4b8fbfb2948c4295c2a34d641dd59a73c512d9fa Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6884 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-03-26tcl/tools: Add function to measure the speed of ARM Cortex-M devicesMarc Schink1-0/+50
Tested on an EFM32PG12 Starter Kit. Change-Id: I2cbc36fe0d2ad2089bf8c1e7d2260daaae4ddbb4 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/5353 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-19tcl/stm32u5x: fix clock config used at 'reset init'Tarek BOCHKATI1-9/+12
Change-Id: If004a04b93be47439809ea3fa336b14de7a12277 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6597 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2022-03-12Remove all occurrences of 'mem2array' and 'array2mem'Marc Schink16-109/+73
Replace deprecated commands 'mem2array' and 'array2mem' with new Tcl commands 'read_memory' and 'write_memory'. Change-Id: I116d995995396133ca782b14cce02bd1ab917a4e Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: https://review.openocd.org/c/openocd/+/6859 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12board: Add LS1046ARDBSean Anderson1-0/+17
This adds support for the LS1046A Reference Design Board. There are several JTAG headers accessable once the case is opened, but this config is for the externally-accessable CMSIS DAP. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I0f83470da3758f0c4512ce47348c4db7de17b27e Reviewed-on: https://review.openocd.org/c/openocd/+/6855 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12target: Add LS1046ASean Anderson1-0/+56
The LS1046A is a quad-core processor from NXP in the layerscape family. This SoC is a bit tricky to program: while the AArch64 CPUs are little-endian, most of the peripherals are big-endian. Care must be taken when interpreting memory reads/writes. This processor is in the same family as the ls1012a, so the setup is similar. If you use OpenOCD to attach early in the boot process, only the cpu0 may be available. Trying to halt other CPUs will fail. To avoid this, defer examination of cpus 1-3, and provide a core_up helper (like e.g. zynqmp). Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54 Reviewed-on: https://review.openocd.org/c/openocd/+/6854 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl: don't use 'set' to retrieve the value of a variableAntonio Borneo4-4/+4
Original TLC syntax uses 'set varname' to retrieve the value of variable 'varname'. Such archaic syntax is still valid, but the shorter '$varname' makes the code easier to read. Replace 'set varname' with '$varname'. While there, remove some useless curly brackets. Change-Id: I27310e8c05afe56ea8bd0e41d4ae2c34447b725c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6863 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2022-03-12tcl/board: Add AM625 EVM basic supportNishanth Menon1-0/+25
Add basic connection details with am625 EVM/SK For further details, see https://www.ti.com/lit/zip/sprr448 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ibd23203ea98e34d03d2f55dac3565aa15aad744b Reviewed-on: https://review.openocd.org/c/openocd/+/6799 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Add AM625 SoCNishanth Menon1-0/+25
Add support for the latest in TI k3 family AM625 SoC. For further details, see https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: Ia54d0eab1c30a973afb1c2c61f4c5a72d29d9b78 Reviewed-on: https://review.openocd.org/c/openocd/+/6798 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/board: Add J721s2 EVM basic supportNishanth Menon1-0/+25
Add basic connection details with J721s2 EVM. For further details, see https://www.ti.com/lit/zip/sprr439 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I68f8818c492ea6e07c14f2da305671c26da801cb Reviewed-on: https://review.openocd.org/c/openocd/+/6797 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Add J721S2 SoCNishanth Menon1-0/+20
Add support for the latest in TI k3 family J721S2 SoC. For further details, see http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd Reviewed-on: https://review.openocd.org/c/openocd/+/6796 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Add a gdb-attach event hook for armv8 and simplify startup ↵Nishanth Menon1-11/+28
function Since we can detect the type of target as well, reuse the _cpu_no_smp_up function name and use the target name to simplify the _up function and maintain consistency with what we introduced for r5. Lets introduce gdb-attach event in a much cleaner fashion. NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior While at it, fix a minor type of s/are/as in "Set Default target are core 0" and simplify the foreach usage. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc Reviewed-on: https://review.openocd.org/c/openocd/+/6616 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Add a gdb-attach event hook for r5 and simplify startup ↵Nishanth Menon1-34/+16
function Since we can detect the type of target as well, make the attach function name generic for the follow on cleanup patch on armv8 to use as well. Lets introduce gdb-attach event in a much cleaner fashion. We can introduce a simpler r5_up function since we now have more descriptive core names making the individual descriptive procs redundant. NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93 Reviewed-on: https://review.openocd.org/c/openocd/+/6617 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Rename R5 targets to be more descriptiveNishanth Menon1-23/+12
R5 targets are currently named r5.0..n and the only way for user to determine the actual type is external documentation. Lets just rename the target names to make them descriptive to not require external documentation for finding which R5 to connect to. NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone for now to allow existing startup proc functions to work, but we will drop it in the follow on patch. Previously: Info : starting gdb server for j721e.cpu.r5.0 on 3336 Info : Listening on port 3336 for gdb connections Info : starting gdb server for j721e.cpu.r5.1 on 3337 Info : Listening on port 3337 for gdb connections Info : starting gdb server for j721e.cpu.r5.2 on 3338 Info : Listening on port 3338 for gdb connections Info : starting gdb server for j721e.cpu.r5.3 on 3339 Info : Listening on port 3339 for gdb connections Info : starting gdb server for j721e.cpu.r5.4 on 3340 Info : Listening on port 3340 for gdb connections Info : starting gdb server for j721e.cpu.r5.5 on 3341 Info : Listening on port 3341 for gdb connections With this patch: Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336 Info : Listening on port 3336 for gdb connections Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337 Info : Listening on port 3337 for gdb connections Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338 Info : Listening on port 3338 for gdb connections Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339 Info : Listening on port 3339 for gdb connections Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340 Info : Listening on port 3340 for gdb connections Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341 Info : Listening on port 3341 for gdb connections Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3 Reviewed-on: https://review.openocd.org/c/openocd/+/6627 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Rename m4 target as general purpose mcuNishanth Menon1-17/+17
The MCU is present on few of the SoCs and is meant as General Purpose (GP) MCU of the system. Lets rename it to make clear what we are debugging - esp when multiple MCUs are present in the system. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152 Reviewed-on: https://review.openocd.org/c/openocd/+/6619 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Rename m3 target as sysctrlNishanth Menon1-16/+16
The M3 is the system controller of the system. Lets rename it to make clear what we are debugging - esp when multiple MCUs are present in the system. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7 Reviewed-on: https://review.openocd.org/c/openocd/+/6618 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Add a gdb-attach event hook for m3 and m4Nishanth Menon1-0/+12
Add gdb-attach event to call the "up" function of m3 and m4 allowing for more seamless integration with gdb for end users. We still retain _up functions for non-gdb functionality. NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior Suggested-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c Reviewed-on: https://review.openocd.org/c/openocd/+/6615 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/target/ti_k3: Remove args from m3 and m4_upNishanth Menon1-2/+2
args serve no purpose, so drop them. Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I136394307016453d576cf524b0f02227ba26ef8a Reviewed-on: https://review.openocd.org/c/openocd/+/6626 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-03-12tcl/stm32l5x|u5x: refactor common tcl codeTarek BOCHKATI3-315/+164
both stm32l5x and stm32u5x configs are almost identical except clock config. while at there rename target procs to avoid issues with JTAG daisy chaining. Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6596 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2022-03-03From upstream (#684)Tim Newsome12-1/+342
* flash/nor/atsame5: add LAN9255 devices Support Microchip LAN9255 devices with embedded SAME53J MCU. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: Ia811c593bf7cf73e588d32873c68eb67c6fafad7 Reviewed-on: https://review.openocd.org/c/openocd/+/6811 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/board: Add EVB-LAN9255 config Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10 connector. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7 Reviewed-on: https://review.openocd.org/c/openocd/+/6812 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * aarch64: support for aarch32 ARM_MODE_UND Fix: unrecognized psr mode: 0x1b cannot read system control register in this mode: (UNRECOGNIZED : 0x1b) Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3 Signed-off-by: Julien Massot <julien.massot@iot.bzh> Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5 Reviewed-on: https://review.openocd.org/c/openocd/+/6808 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Combine register lists of smp targets. This is helpful when you want to pretend to gdb that your heterogeneous multicore system is homogeneous, because gdb cannot handle heterogeneous systems. This won't always works, but works fine if e.g. one of the cores has an FPU while the other does not. (Specifically, HiFive Unleashed has 1 core with no FPU, plus 4 cores with an FPU.) Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0 Reviewed-on: https://review.openocd.org/c/openocd/+/6362 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * semihosting: use open mode flags from GDB, not from sys/stat.h Values defined in sys/stat.h are not guaranteed to match the constants defined by the GDB remote protocol, which are defined in https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags. On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is defined as 0x40, whereas GDB requires it to be 0x400, causing all "w" file open modes to misbehave. This patch has been tested with STM32F446. Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910 Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6804 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * semihosting: User defined operation, Tcl command exec on host Enabling a portion (0x100 - 0x107) of the user defined semihosting operation number range (0x100 - 0x1FF) to be processed with the help of the existing target event mechanism, to implement a general-purpose Tcl interface for the target available on the host, via semihosting interface. Example usage: - The user configures a Tcl command as a callback for one of the newly defined events (semihosting-user-cmd-0x10X) in the configuration file. - The target can make a semihosting call with <opnum>, passing optional parameters for the call. If there is no callback registered to the user defined operation number, nothing happens. Example usage: Configure RTT automatically with the exact, linked control block location from target. Signed-off-by: Zoltán Dudás <zedudi@gmail.com> Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247 Reviewed-on: https://review.openocd.org/c/openocd/+/6748 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/smp: use a struct list_head to hold the smp targets Instead of reinventing a simply linked list, reuse the list helper for the list of targets in a smp cluster. Using the existing helper, that implements a double linked list, makes trivial going through the list in reverse order. Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6783 Tested-by: jenkins * helper/list: add list_for_each_entry_direction() Use a bool flag to specify if the list should be forward or backward iterated. Change-Id: Ied19d049f46cdcb7f50137d459cc7c02014526bc Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6784 Tested-by: jenkins * target/riscv: revive 'riscv resume_order' This functionality was lost in [1], which was merged as commit 615709d14049 ("Upstream a whole host of RISC-V changes."). Now it works as expected again. Add convenience macro foreach_smp_target_direction(). Link: [1] https://github.com/riscv/riscv-openocd/pull/567 Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6785 Tested-by: jenkins * doxygen: fix some function prototype description Change-Id: I49311a643ea73143839d2f6bde976cfd76f8c67f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6830 Tested-by: jenkins * Cadence virtual debug interface (vdebug) integration Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6097 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * gdb_server: Include thread name as XML attribute Explicitly providing a thread name in the "thread" element produces better thread visualizations in downstream tools like IDEs. Signed-off-by: Ben McMorran <bemcmorr@microsoft.com> Change-Id: I102c14ddb8b87757fa474de8e3a3f6a1cfe10d98 Reviewed-on: https://review.openocd.org/c/openocd/+/6828 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Fix small memory leak. See https://github.com/riscv/riscv-openocd/pull/672 Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6831 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * server: remove remaining crust from dropped eCos code Commit 39650e2273bc ("ecosboard: delete bit-rotted eCos code") has removed eCos code but has left some empty function that was used during non-eCos build to replace eCos mutex. Drop the functions and the file that contain them. Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6835 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * rtos: threadx: Add hla_target support for ThreadX Tested with an AZ3166 dev board (which uses the STM32F412ZGT6) running the Azure RTOS ThreadX demonstration system. Signed-off-by: Ben McMorran <bemcmorr@microsoft.com> Change-Id: I44c8f7701d9f1aaa872274166321cd7d34fb1855 Reviewed-on: https://review.openocd.org/c/openocd/+/6829 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * .gitmodules: switch away from repo.or.cz The host repo.or.cz is often offline, creating issues for cloning and building OpenOCD from scratch. Already 'jimtcl' developer has dropped repo.or.cz, triggering the OpenOCD commit 861e75f54efb ("jimtcl: switch to github"). Change also the link of the remaining submodules 'git2cl' and 'libjaylink' to their respective main repository. Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6834 Tested-by: jenkins Reviewed-by: zapb <dev@zapb.de> * flash/nor/stm32f2x: Fix erase of bank 2 sectors This commit corrects the erase function for stm32f2x when dealing with sectors in bank 2, for STM32F42x/43x devices with 1MB flash. On STM32F42x/43x with 1MB flash in dual bank configuration, the sector numbering is not consecutive. The last sector in bank 1 is number 7, and the first sector in bank 2 is number 12. The sector indices used by openocd, however, _are_ consecutive (0 to 15 in this case). The arguments "first" and "last" to stm32x_erase() are of this type, and so the logic surrounding sector numbers needed to be corrected. Since the two banks in dual bank mode have the same number of sectors, a sector index in bank 2 is larger than or equal to half the total number of sectors. Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18 Signed-off-by: Simon Johansson <ampleyfly@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6810 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * target/cortex_m: fix target_to_cm() helper The third parameter of container_of() should point to the same member as target->arch_info points to, struct arm. It worked just because struct arm is the first member in struct armv7m_common. If you move arm member from the first place, OpenOCD fails heavily. Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6749 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/armv7m,cortex_m: introduce checked arch_info cast routines target_to_armv7m() and target_to_cm() do not match the magic number so they are not suitable for use outside of target driver code. Add checked versions of pointer getters. Match the magic number to ensure the returned value points to struct of the correct type. Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6750 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target/cortex_m: add Cortex-M part number getter The getter checks the magic numbers in arch_info to detect eventual type mismatch. Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: https://review.openocd.org/c/openocd/+/6751 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * flash/nor/stm32xx: fix segfault accessing Cortex-M part number Some of STM32 flash drivers read Cortex-M part number from cortex_m->core_info. In corner cases the core_info pointer was observed uninitialised even if target_was_examined() returned true. See also [1] Use the new and safe helper to get Cortex-M part number. While on it switch also target_to_cm()/target_to_armv7m() to the safe versions. This prevents a crash when the flash bank is misconfigured with non-Cortex-M target. Add missing checks for target_was_examined() to flash probes. [1] 6545: fix crash in case cortex_m->core_info is not set https://review.openocd.org/c/openocd/+/6545 Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Fixes: f5898bd93ff8 (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common) Reviewed-on: https://review.openocd.org/c/openocd/+/6752 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> * cpld: altera-epm240: Add additional IDCODEs This adds some additional IDCODEs from the datasheet. It also adds support for customizing the tap name. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * cpld: altera-epm240: Increase adapter speed According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target: Add support for ls1088a The LS1088A is an octo-core aarch64 processor from NXP in the layerscape family. The JTAG is undocumented, but I was able to figure things out from the output of `dap info`. This is the first in-tree example of using the hwthread rtos (as far as I know), so hopefully it can serve as an example to other developers. There are some ETMs, but I was unable to try them out because I got 'invalid command name "etm"' when trying to test things out. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2 Reviewed-on: https://review.openocd.org/c/openocd/+/6848 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * target: ls1088a: Add service processor Normally the service processor is not necessary for debugging. However, if you are using the hard-coded RCW or your boot source is otherwise corrupt, then the general purpose processors will never be released from hold-off. This will cause GDB to become confused if it tries to attach, since they will appear to be running arm32 processors. To deal with this, we can release the CPUs manually with the BRRL register. This register cannot be written to from the axi target, so we need to do it from the service processor target. This involves halting the service processor, modifying the register, and then resuming it again. We try and determine what state the service processor was in to avoid resuming it if it was already halted. The reset vector for the general purpose processors is determined by the boot logation pointer registers in the device configuration unit. Normally these are set using pre-boot initialization commands, but if they are not set then they default to 0. This will cause the CPU to almost immediately hit an illegal instruction. This is fine because we will almost certainly want to attach to the processor and load a program anyway. I considered adding this as an event handler for either gdb-attach or reset-init. However, this command shouldn't be necessary most of the time, and so I don't think we should run it automatically. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c Reviewed-on: https://review.openocd.org/c/openocd/+/6850 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * board: Add NXP LS1088ARDB This adds a board file for the NXP LS1088ARDB. This only covers the "primary" JTAG header J55, and not the PCIe header (J91). The only oddity is that the LS1088A and CPLD are muxed by adding/removing a jumper from J48. Unfortunately, it doesn't look like OpenOCD supports this CPLD beyond determining the irlen, so it's not very useful. Those who are interested in experimenting can define CWTAP to access the CPLD, but the default is to access the CPU. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24 Reviewed-on: https://review.openocd.org/c/openocd/+/6849 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * gdb_server: fix double free Commit 6541233aa78d ("Combine register lists of smp targets.") unconditionally assigns the output pointers of the function smp_reg_list_noread(), even if the function fails and returns error. This causes a double free from the caller, that has assigned NULL to the pointers to simplify the error handling. Use local variables in smp_reg_list_noread() and assign the output pointers only on success. Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6852 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com> * gdb_server: check target examined while combining reg list Commit 6541233aa78d ("Combine register lists of smp targets.") assumes that all the targets in the SMP cluster are already examined and unconditionally call target_get_gdb_reg_list_noread() that will in turn return error if the target is not examined yet. Skip targets not examined yet. Add an additional check in case the register list cannot be built, e.g. because no target in the SMP cluster is examined. This should never happen, but it's better to play safe. Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a Fixes: 6541233aa78d ("Combine register lists of smp targets.") Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6853 Tested-by: jenkins Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com> Reviewed-by: Tim Newsome <tim@sifive.com> * flash/stm32l4x: fix maybe-uninitialized compiler error using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get: error: ‘retval’ may be used uninitialized in this function fixes: 13cd75b6ecfd (flash/nor/stm32xx: fix segfault accessing Cortex-M part number) Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6861 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Fix build. Change-Id: Ia60246246dd859d75659a43d1c59588dbb274d46 Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Co-authored-by: Julien Massot <julien.massot@iot.bzh> Co-authored-by: Pavel Kirienko <pavel.kirienko@gmail.com> Co-authored-by: Zoltán Dudás <zedudi@gmail.com> Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com> Co-authored-by: Jacek Wuwer <jacekmw8@gmail.com> Co-authored-by: Ben McMorran <bemcmorr@microsoft.com> Co-authored-by: Simon Johansson <ampleyfly@gmail.com> Co-authored-by: Tomas Vanek <vanekt@fbl.cz> Co-authored-by: Sean Anderson <sean.anderson@seco.com> Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2022-02-26board: Add NXP LS1088ARDBSean Anderson1-0/+14
This adds a board file for the NXP LS1088ARDB. This only covers the "primary" JTAG header J55, and not the PCIe header (J91). The only oddity is that the LS1088A and CPLD are muxed by adding/removing a jumper from J48. Unfortunately, it doesn't look like OpenOCD supports this CPLD beyond determining the irlen, so it's not very useful. Those who are interested in experimenting can define CWTAP to access the CPLD, but the default is to access the CPU. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24 Reviewed-on: https://review.openocd.org/c/openocd/+/6849 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26target: ls1088a: Add service processorSean Anderson1-0/+32
Normally the service processor is not necessary for debugging. However, if you are using the hard-coded RCW or your boot source is otherwise corrupt, then the general purpose processors will never be released from hold-off. This will cause GDB to become confused if it tries to attach, since they will appear to be running arm32 processors. To deal with this, we can release the CPUs manually with the BRRL register. This register cannot be written to from the axi target, so we need to do it from the service processor target. This involves halting the service processor, modifying the register, and then resuming it again. We try and determine what state the service processor was in to avoid resuming it if it was already halted. The reset vector for the general purpose processors is determined by the boot logation pointer registers in the device configuration unit. Normally these are set using pre-boot initialization commands, but if they are not set then they default to 0. This will cause the CPU to almost immediately hit an illegal instruction. This is fine because we will almost certainly want to attach to the processor and load a program anyway. I considered adding this as an event handler for either gdb-attach or reset-init. However, this command shouldn't be necessary most of the time, and so I don't think we should run it automatically. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c Reviewed-on: https://review.openocd.org/c/openocd/+/6850 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26target: Add support for ls1088aSean Anderson1-0/+42
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape family. The JTAG is undocumented, but I was able to figure things out from the output of `dap info`. This is the first in-tree example of using the hwthread rtos (as far as I know), so hopefully it can serve as an example to other developers. There are some ETMs, but I was unable to try them out because I got 'invalid command name "etm"' when trying to test things out. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2 Reviewed-on: https://review.openocd.org/c/openocd/+/6848 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26cpld: altera-epm240: Increase adapter speedSean Anderson1-0/+4
According to the datasheet, the minimum clock period with Vccio1 = 1.5V (the lowest voltage supported) is 143ns, or around 6MHz. Set the default adapter speed to 5 MHz. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de Reviewed-on: https://review.openocd.org/c/openocd/+/6847 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-26cpld: altera-epm240: Add additional IDCODEsSean Anderson1-1/+14
This adds some additional IDCODEs from the datasheet. It also adds support for customizing the tap name. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e Reviewed-on: https://review.openocd.org/c/openocd/+/6846 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-02-14Cadence virtual debug interface (vdebug) integrationJacek Wuwer8-0/+225
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6097 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: zapb <dev@zapb.de> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-29tcl/board: Add EVB-LAN9255 configHans-Erik Floryd1-0/+11
Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10 connector. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7 Reviewed-on: https://review.openocd.org/c/openocd/+/6812 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2022-01-28Merge branch 'master' into from_upstreamTim Newsome1-0/+2
Change-Id: I61e24edbdeceddba265514fd7e0a489ec23e2a4c
2022-01-05flash/nor/efr32: fixed lockbits and user dataDoug Brunner1-0/+2
Changed flash driver to support writing to the user data page, as well as to any portion of the lockbits page above 512 bytes (the amount used for the actual page lock words). The top part of the lockbits page is used on at least the EFR32xG1 chips for the SiLabs bootloader encryption keys. As presented to the user, the lockbits page is the same size as the other pages, but any attempt to write to its low 512 bytes is an error. To enforce this, efr32x_write is renamed to efm32x_priv_write and a wrapper function is provided in its place. If the user erases the lockbits page, the driver rewrites the cached lock words after the erase. When the driver erases the lockbits page in order to update the lock words, it first takes a copy of anything stored in the top part of the page, and re-programs it after the erase operation. There are now multiple instances of flash_bank for each target, and the flash_bank instances must share their cached lock words to operate as intended. Therefore, when a bank is created, the global flash bank list is used to find any other banks that share the same target. Since some banks in the global list are invalid at the time free_driver_priv is called, reference counting is used to decide when to free driver_priv. To avoid the need to find the lockbits flash_bank from another flash_bank, efm32x_priv_write and efm32x_erase_page now take an absolute address. There didn't seem to be any reason to prohibit unprotecting individual flash pages, so that limitation is removed from efm32x_protect(). This addresses ticket #185. Valgrind-clean, except for 2x 4kiB not freed/still reachable blocks that were allocated by libudev. No new Clang analyzer warnings, no new sanitizer warnings. Signed-off-by: Doug Brunner <doug.a.brunner@gmail.com> Change-Id: Ifb22e6149939d893f386706e99b928691ec1d41b Reviewed-on: https://review.openocd.org/c/openocd/+/6665 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik.hederstierna@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-12-28Merge branch 'master' into from_upstreamTim Newsome3-0/+124
Conflicts: doc/openocd.texi src/flash/nor/fespi.c Change-Id: Iaac61cb6ab8bba9df1d4b9a52671a09163eb50b2
2021-12-14Handle changed `ftdi` syntax. (#670)Tim Newsome5-39/+39
Also rename ftdi_oscan1_mode command which only exists in our branch. Change-Id: Ie9b28f228b1fd984244edb8162d552104d28e462 Signed-off-by: Tim Newsome <tim@sifive.com>
2021-12-11Add Microchip SAME51 Curiosity Nano boardJoerg Wunsch1-0/+14
This board is (software wise) similar to the existing SAME54 Xplained Pro board, with just a slightly different MCU. (Hardware wise, it features a vastly different form factor.) Signed-off-by: Jörg Wunsch <openocd@uriah.heep.sax.de> Change-Id: I5e5435d49d333fb74471994ee84de59ed983153c Reviewed-on: https://review.openocd.org/c/openocd/+/6747 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Axel W. Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-12-03tcl: stm32mp13x: add target and board config filesAntonio Borneo2-0/+110
The stm32mp13x has one core Cortex-A7. The board Discovery Kit includes an on-board STLink-V3 with SWD connection. The webpage of the board is not active yet. Change-Id: I8836b26612a160ead79766955ebefaf3d21a329c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6675 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
2021-11-30Merge branch 'master' into from_upstreamTim Newsome10-9/+83
Merged 1ad6ed38b6da09b1d5d9e56d1344fced2dce12bc Conflicts: src/rtos/rtos_standard_stackings.c Change-Id: Ica8109135de0f9aa87455353a4538b161b844b04
2021-11-28jtag/hla, jtag/stlink: switch to command 'adapter serial'Antonio Borneo3-3/+3
The driver hla defines the command 'hla_serial' to specify the serial string of the adapter. The driver st-link defines the command 'st-link serial' to specify the serial string of the adapter. Remove and deprecate the driver commands and use 'adapter serial'. Change-Id: I9505c398a77125b1ebf4ba71da7baf4d663b75be Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6657 Tested-by: jenkins
2021-11-28jtag/jlink: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver jlink defines the command 'jlink serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Note: in former code the commands 'jlink serial' and 'jlink usb' were mutually exclusive; running one of them would invalidate the effect of a previous execution of the other. The new code gives priority to 'adapter serial', even if executed before 'jlink usb'. Change-Id: I920b0c136716f459b6fd6f7da8a01a7fa1ed389f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6656 Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2021-11-28jtag/xds110: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver xds110 defines the command 'xds110 serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Note: the original command 'xds110 serial' used a complex and undocumented conversion of the serial number through multibyte string, wide-character string and C cast. The XDS110 I can access and the lsusb dumps available through Google don't show any exotic USB serial that require such conversion. The original developer doesn't remember any constraint that mandates such conversion (see comments in https://review.openocd.org/4322/). The conversion is removed by this patch. Change-Id: I38909918079b2c1797ad85ebec2fea1b33743606 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6655 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-28jtag/kitprog: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver kitprog defines the command 'kitprog_serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I844cb815af01137392b6d12e1b5972fc77ac092d Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6652 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-28jtag/ftdi: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver ftdi defines the command 'ftdi serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: Ia5b1f325b9fab8f58b5ea70f8b807e50b148b939 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6651 Tested-by: jenkins
2021-11-28jtag/cmsis_dap: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver cmsis_dap defines the command 'cmsis_dap_serial' to specify the serial string of the adapter. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I88e2d4de360a6c6f23529bb18494962a267250df Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6649 Tested-by: jenkins
2021-11-28jtag/aice: switch to command 'adapter serial'Antonio Borneo1-1/+1
The driver aice defines the command 'aice serial' to specify the serial string of the adapter, but actually does not use this value in the code. Remove and deprecate the driver command, and use 'adapter serial'. Change-Id: I892e0a4e1b41a7a87adf54a5736abf7419f32979 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6648 Tested-by: jenkins
generated by cgit v1.1 at 2024-09-18 08:20:18 +0000