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2023-02-10CSR_MCOUNTEREN should not exist if U-mode is not supportedParshintsev Anatoly1-0/+3
Change-Id: I1a2420fb88bd3ee37f6a539992e8dc119fdd6e0e
2023-02-08Print out debug value after the assignment is made.Tim Newsome1-1/+1
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
2023-02-08Move yes_no_maybe_t into riscv.h.Tim Newsome2-6/+6
Change-Id: I5bbdc1af3147e05e25612bf496f409111248c979
2023-02-08Improve a debug log in freertos_update_threads()duchao1-1/+1
To make the log more accurate and comprehensible. In case the offset is non-zero. Signed-off-by: Chao Du <duchao@eswincomputing.com>
2023-02-01Fix opcode for the "fence" instructionJan Matyas4-7/+8
OpenOCD currently uses improper "fence" instruction: "FENCE" opcode with empty predecessor and successor sets. Such instruction has no effect and is reserved for future use as a HINT instruction (RISC-V Unprivileged ISA spec V20191213, section 2.9). This patch fixes it by using the proper "fence rw,rw" instruction. Change-Id: Ia2a66059009153efef27279410850ddfd73dae38 Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
2023-01-10target/riscv: added support for missing VCSR registerParshintsev Anatoly3-0/+3
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2023-01-04Merge pull request #777 from riscv/itriggerTim Newsome2-22/+289
target/riscv: Add `riscv` `itrigger` and `etrigger` commands.
2023-01-03target/riscv: Remove `riscv test_sba_config_reg` command. (#780)Tim Newsome3-404/+0
This command is supposed to be a start at a compliance test for system bus access. It doesn't pass against spike because it doesn't handle all cases where the interface might be busy. It's not documented. As far as I know nobody uses it. So delete 400 lines of code instead of trying to fix it. Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03target/riscv: Use unsigned int for trigger indexes.Tim Newsome1-7/+12
Change-Id: I1f7cf3a5c8b86f3d6825f45a67ff05822ea67d28 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-03target/riscv: Read back tdata2 in set_trigger()Tim Newsome1-4/+14
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6 Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02target/riscv: Add `riscv etrigger` command.Tim Newsome2-0/+118
Change-Id: I7982231c5067b82e4ddb2999bca51dba06ccac7a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-02target/riscv: Add `riscv itrigger` command.Tim Newsome2-7/+141
This lets the user set an itrigger trigger, which doesn't fit in the normal breakpoint abstraction. This implementation only allows control of a single itrigger. Hardware could support more than one, and that may be useful to catch different interrupts in different execution modes. But it would make the code/UI more complex and it feels like an unlikely use case. Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27target/riscv: Use macros for trigger types.Tim Newsome1-6/+6
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf Signed-off-by: Tim Newsome <tim@sifive.com>
2022-12-27flash: fix clang static analyzer build errors (#778)Tim Newsome2-5/+0
Fixes "variable set but not used" errors. Tested with Homebrew clang version 13.0.1 Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Change-Id: Ia90baf5b4857db2b5569ebe6adbbb832de772aad Reviewed-on: https://review.openocd.org/c/openocd/+/6971 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com> Co-authored-by: Erhan Kurubas <erhan.kurubas@espressif.com>
2022-12-02riscv/run_algorithm : Add support for memory parameters (#773)Dolu19901-5/+27
* riscv/run_algorithm : Add support for memory parameters Change-Id: I5045a3843dcd96edb0cf8cc54bbd41969e3260a6 Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * riscv/run_algorithm : better parameter handeling Change-Id: If3da8b83f784ef7b13ca83e98bc629e2219cc632 Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> * riscv/run_algorithm : Better mem param error reporting Change-Id: I09f99ca117f7e5373b23cad0f69d9d5b2a77e61d Signed-off-by: Dolu1990 <charles.papon.90@gmail.com> Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
2022-11-29target/riscv: Set target->state in riscv013_halt_go()Tim Newsome1-2/+14
Then also set it when we resume in examine(), which doesn't use the full abstractions because not all required data structures are filled out yet. Hopefully fixes #749. Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23target/riscv: Fix small riscv013_halt_go() bugTim Newsome1-1/+1
Exit the loop when no harts are running, instead of when at least one hart has halted. Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAKTim Newsome3-4/+4
Simple rename to make code slightly more clear. Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-23target/riscv: Set correct target->state in riscv013_halt_go()Tim Newsome1-3/+26
It used to set all states to halted, but that's not right for harts that are now unavailable. (It might be possible to call poll() at the right time instead of duplicating some of its code, but I didn't see an easy way to do that. The real requirement is that target->state is set to TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in halt_finish(), because that's what triggers hwthread_update_threads(), which must know about unavailable harts so they can be hidden from gdb. Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22gdb_server: Operate on available targets.Tim Newsome1-16/+40
When SMP is enabled, gdb will always use the first target in the SMP group. That doesn't work when that first target is unavailable, but others in the SMP group are still available. For cases where gdb expects an operation to affect the entire group (run control, memory access), find the first available target in an SMP group and use that. Change-Id: I4bed600da3ac0fdfe4287d8fdd090a58452db501 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22target/riscv: Don't resume unavailable harts.Tim Newsome2-7/+19
Change-Id: I30a2e9ec6c1b99fb92ab1a160ddb63682167c6d8 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22target/riscv: Share single-target and SMP resume code.Tim Newsome1-30/+33
Change-Id: I416d8cc4c8c5ca0337c1f7e392b6b4fa3d75757f Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22rtos/hwthread: Hide unavailable targets from thread list.Tim Newsome1-2/+4
Change-Id: I53c6e2876d9bab70800a0f080e72a2abe0499120 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-22target/riscv: Make poll() use TARGET_UNAVAILABLE.Tim Newsome2-60/+152
Change-Id: I7052dd08581f0ce6a05cd8319e9bec0086296fc3 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21target/riscv: Refactor riscv_openocd_poll()Tim Newsome1-101/+74
There used to be entirely separate code paths depending on whether we're in SMP mode or not. Now they're both the same. Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21target/riscv: Error when hart becomes unavailable during resumeTim Newsome1-0/+2
Change-Id: I731e6178b2b08b65206614b0dc2a0d993c149cc3 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-21Merge pull request #769 from riscv/0.11Tim Newsome2-27/+22
Revive 0.11 debug spec support
2022-11-17target/riscv: 0.11, call handle_halt() after stepTim Newsome1-1/+3
This ensures that we populate the register cache and set target->state. Some RISC-V changes had upset the balance. Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-17target/riscv: Ignore maskmax when reading back tdata1Tim Newsome1-15/+18
We don't correctly write it, so we shouldn't expect it to read back the same value. Fixes hardware breakpoints on mcontrol triggers. Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
2022-11-17target/riscv: Don't always read on DMI batch write (#768)Tim Newsome3-13/+19
Indicate to the JTAG driver that it does not need to read and return the DR register value after scanning the JTAG chain. riscv_batch_run(), calls jtag_add_dr_scan() to schedule a DR scan operation. Eventually, this will result in the JTAG driver performing a JTAG scan to write to or read from DR. The decision on whether to write to and/or read from DR register is determined by the second parameter to jtag_add_dr_scan(), i.e. a "struct scan_field". Of particular interest here is if batch->fields[i]->in_value is not NULL, the JTAG developer must return the DR value collected from the JTAG scan operation. When creating the DR scan operation instruction with riscv_batch_add_dmi_write(), batch->fields[i]->in_value points to a location in batch->data_in buffer, meaning batch->field[i]->in_value is not NULL, and the JTAG developer must therefore read and return the DR value collected. The returning of the DR value is redundant in a write operation. This patch set batch->fields[i]->in_value to NULL to indicate the DR value need not be returned. This allows the JTAG developer to optimize away any code associated with returning the DR value. Normally, the extra work to return the DR value is negligible. However, in one usecase it introduces significant delays In this use case a JTAG driver forwards all JTAG scan to a server on a network. If the server has to return the DR value, it has to perform the JTAG scan before replying to the JTAG driver, and only then the JTAG driver can send the next JTAG scan operation. However, if there is no need to return the DR value, the server can acknowledge the JTAG operation request immediately,thus signalling to the JTAG driver that it is free to send the next JTAG scan operation. At the same time of receiving the second JTAG operation the server will process the original JTAG scan. This saves time and mitigates network delay. Also, not having to include the DR value in resulting in smaller reply packet from server to JTAG driver and save on network traffic. This doubles download speeds to spike using remote bitbang. Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
2022-11-17target/riscv: Ignore debug_execution in 0.11 resumeTim Newsome1-11/+1
It's only used to change what callback events are generated, and there are none anyway. (That's probably a bug, but since 0.11 is so rare I'm not going to worry about it.) Fixes #757. Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-16Fix breackpoint_add for rtos swbp (#734)Evgeniy Naydanov2-14/+11
breakpoint_add should use rtos only if request is done by gdb. Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-15Workaround for fp register access in case fp unit is disabled (#766)Evgeniy Naydanov1-11/+11
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus set to 0), accessing any fp register results in a hang (any abstract command timeouts, untill the board is rebooted). Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2022-11-10Improve a couple of user/debug messages. (#763)Tim Newsome2-2/+3
* gdb_server: Improve info message. Add target name and state to "Not running when halt was requested" message. Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd Signed-off-by: Tim Newsome <tim@sifive.com> * rtos/hwthread: Nicer debug message in hwthread_update_threads() Change-Id: Ia5931a772476a2ae186ed87cd70d7e4be2f196fb Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10target/riscv: Use vlenb to check whether vector registers exist (#762)Tim Newsome3-24/+13
E.g. the Zve* vector extensions have all the same registers as the full V extension, but leaves misa.V clear. Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-10riscv/target: Replace is_halted() with get_hart_state() (#756)Tim Newsome3-61/+84
Prep work for handling unavailable harts. Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028 Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com>
2022-11-09Use match field for trigger (#725)Xiang W3-193/+305
* Use match field for trigger The watchpoint cannot capture all data modifications only through the trigger of ANY SIZE and EQUAL, and an error will occur. This patch accommodates watchpoints by adding more types of matches Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a Signed-off-by: Xiang W <wxjstz@126.com> * Add variable type trigger support Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1 Signed-off-by: Xiang W <wxjstz@126.com> * remove trailing whitespace Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84 Signed-off-by: Xiang W <wxjstz@126.com> * update triggers enumerate Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-09target/riscv: Deal with DMI busy in sample_memory_bus_v1() (#758)Tim Newsome1-5/+16
* target/riscv: Deal with DMI busy in sample_memory_bus_v1() Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231 Signed-off-by: Tim Newsome <tim@sifive.com> * Comment code more clearly. Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Remove extra tab Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-11-01Fix dm->current_hartid corruption on hartsellen discovery (#754)Dolu19901-1/+9
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2 Signed-off-by: Charles Papon <charles.papon.90@gmail.com> * target/riscv Ensure HART_INDEX_DIRTY does not have side effects Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027 Signed-off-by: Charles Papon <charles.papon.90@gmail.com> Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
2022-10-27target: Add TARGET_UNAVAILABLE state. (#752)Tim Newsome2-0/+4
This is added for future RISC-V changes. The RISC-V debug interface can explicitly tell a debugger when a hart is unavailable. This is used for instance when that hart is powered down (or yet to be powered up out of reset). Change-Id: I8a062d59eea1e5b3c788281a75159592db024683 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-21target/riscv: Correctly set target->state in deassert_reset (#750)Tim Newsome1-2/+7
* target/riscv: Correctly set target->state in deassert_reset This bug didn't lead to problems, but it would with some upcoming changes. Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb Signed-off-by: Tim Newsome <tim@sifive.com> * Keep debug_reason in sync with state Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-14[riscv] step operation handler should respect handle_breakpoints parameter ↵Anatoly Parshintsev1-3/+22
(#741) * [riscv] step operation handler should respect handle_breakpoints parameter When step operation is requested the OpenOCD frontend (like gdb server or TCL server) has an option to control how existing breakpoints are handled upon step. Some OpenOCD frontends (like gdbserver) may choose to disable special handling of existing breakpoints - thus handle_breakpoints is set to 0, while others (like TCL server) expect target handler to temporary disable the matching breakpoint to allow the step operation to complete successfully. In the current implementation handle_breakpoints parameter was ignored by target-specific handler. Thus, the following sequence of commands: ``` halt bp <current_pc> 4 step ``` Resulted in *step* operation to not change PC because of bp match. This commit addresses this issue. * Adjusted calls to logging facilities (addressed review comments) Co-authored-by: Tim Newsome <tim@sifive.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com> Co-authored-by: Tim Newsome <tim@sifive.com>
2022-10-12Properly track selecting multiple harts at once. (#743)Tim Newsome1-59/+64
* Properly track selecting multiple harts at once. use_hasel is a bit of a hack. Change-Id: Ia589ebc16bca32038d915df9988361b88e940917 Signed-off-by: Tim Newsome <tim@sifive.com> * Clarifying comment. Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Rename set_hartsel to set_dmcontrol_hartsel Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850 * Make set_dmcontrol_hartsel() more idiomatic. Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486 * Use constant for multiple harts instead of -1. Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb Signed-off-by: Tim Newsome <tim@sifive.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2022-10-11target/riscv: Clean up halt_go for multiple harts.Tim Newsome1-6/+11
Also add an early exit for if any harts are unavailable. Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-10Merge pull request #745 from dmitryryzhov/fix-bracesTim Newsome1-2/+2
Fix incorrect braces caused by #732
2022-10-07(Re)Init cJTAG before move JTAG to reset statemrv961-1/+1
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
2022-10-07(Re)Init cJTAG only after trst (not after srst)mrv961-4/+5
2022-10-07Fix incorrect braces caused by #732Dmitry Ryzhov1-2/+2
2022-10-05riscv: Minor formatting cleanup.Tim Newsome1-9/+7
Change-Id: I0256fd047d8369ca7b327172225a9d1f827673c5 Signed-off-by: Tim Newsome <tim@sifive.com>
2022-10-05Use TMSC_EN signal for cJTAG escape seq if definedmrv961-0/+5
Signed-off-by: mrv96 <mrv96@users.noreply.github.com>
generated by cgit v1.1 at 2024-10-13 15:47:37 +0000