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AgeCommit message (Expand)AuthorFilesLines
2017-04-10riscv: Implement the assert/deassert reset functions for v13Megan Wachs2-2/+11
2017-04-04riscv: move value read to after autoexec is cleared.Megan Wachs1-8/+15
2017-04-04riscv: Correct the autoexec in read_memMegan Wachs1-4/+13
2017-04-02aarch64: clear CTI halt event early at debug entryMatthias Welwarsky1-0/+2
2017-03-30riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.Megan Wachs1-9/+5
2017-03-23Don't set abstractauto at the startPalmer Dabbelt1-1/+2
2017-03-22riscv: Retry failed memory readsMegan Wachs1-65/+75
2017-03-21riscv: add missing variable declaration.Megan Wachs1-0/+1
2017-03-21Clear autoexec correctlyPalmer Dabbelt1-1/+1
2017-03-21Wrong autoexecPalmer Dabbelt1-2/+2
2017-03-21BuildsPalmer Dabbelt2-425/+533
2017-03-15riscv-v13: wait for idle in read_memoryMegan Wachs1-3/+10
2017-03-06arm_dpm: fix dpm setupGirts Folkmanis1-1/+1
2017-02-27Remove more cruft.Tim Newsome1-35/+1
2017-02-27riscv: Ensure that hart is halted before attempting to examine it.Megan Wachs1-2/+4
2017-02-25Remove cruft.Tim Newsome1-47/+11
2017-02-25Use DCSR constants from the debug spec.Tim Newsome1-170/+21
2017-02-25Update bits to latest spec.Tim Newsome2-587/+591
2017-02-24armv8_dpm: fix exception handlingMatthias Welwarsky1-0/+2
2017-02-24armv8_dpm: retrieve only necessary registers on haltMatthias Welwarsky1-3/+11
2017-02-24armv8: spelling and formatting updatesMatthias Welwarsky1-9/+4
2017-02-24aarch64: run control reworkMatthias Welwarsky3-295/+614
2017-02-24aarch64: clean up struct aarch64_commonMatthias Welwarsky2-21/+14
2017-02-24aarch64: clean up target specific commandsMatthias Welwarsky1-7/+2
2017-02-24aarch64: reset fixesMatthias Welwarsky1-2/+11
2017-02-24armv8: factor out generic bit set/clr for debug registersMatthias Welwarsky3-17/+23
2017-02-24armv8: load aarch32 register through aarch64 equivalentMatthias Welwarsky1-6/+3
2017-02-24aarch64: remove bogus address check before memory accessMatthias Welwarsky1-13/+0
2017-02-24target: generic ARM CTI function wrapperMatthias Welwarsky3-2/+225
2017-02-24aarch64: optimize core state detectionMatthias Welwarsky1-8/+2
2017-02-24aarch64: reduce debug output to improve legibilityMatthias Welwarsky3-28/+0
2017-02-24aarch64: remove mrs/msr functions from struct armMatthias Welwarsky2-70/+0
2017-02-24aarch64: refactor SCTLR manipulationMatthias Welwarsky2-135/+98
2017-02-24aarch64: fix software breakpoints when in aarch32 stateMatthias Welwarsky5-6/+31
2017-02-22Speed things up by ignoring return values.Tim Newsome1-13/+45
2017-02-21Optimize memory write code, used in download.Tim Newsome1-92/+216
2017-02-20Better error checking in memory access.Tim Newsome1-4/+8
2017-02-20Properly restore s0 and s1 on resume.Tim Newsome1-8/+8
2017-02-17Fix access FPU registers again.Tim Newsome1-46/+80
2017-02-17Fix use of REG vs CSR constants.Tim Newsome1-26/+30
2017-02-17Bunch of register access refactoring.Tim Newsome2-546/+161
2017-02-16Check busy before triggering another command.Tim Newsome1-46/+50
2017-02-15Check for errors after read/write.Tim Newsome1-4/+12
2017-02-15Fix double read, which might have side effects.Tim Newsome1-4/+6
2017-02-15Make MemTest32 pass.Tim Newsome1-2/+2
2017-02-15Some memory access works.Tim Newsome2-351/+161
2017-02-15aarch64: Fix #include guardsMarc Schink2-4/+4
2017-02-14Merge pull request #15 from sifive/get_set_reg_errorTim Newsome1-3/+14
2017-02-14Make general CSR reads work.Tim Newsome1-36/+22
2017-02-14Make it all the way through examine().Tim Newsome1-220/+85
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