aboutsummaryrefslogtreecommitdiff
path: root/src/target/riscv
AgeCommit message (Expand)AuthorFilesLines
2024-04-14Merge pull request #1040 from rivos-eblot/dev/ebl/read_mem_dmibaseEvgeniy Naydanov1-1/+5
2024-04-14Merge pull request #1023 from en-sc/en-sc/check-ac-busyEvgeniy Naydanov1-80/+239
2024-04-11target/riscv: check `abstractcs.busy`Evgeniy Naydanov1-6/+73
2024-04-11target/riscv: introduce `examine_dm()` functionEvgeniy Naydanov1-73/+131
2024-04-10target/riscv: cache `abstractcs.busy` in `dm013_info_t`Evgeniy Naydanov1-2/+36
2024-04-05target/riscv: read registers are not valid on a running targetEvgeniy Naydanov1-1/+2
2024-04-04target/riscv: Add missing DM base offset to read_memory_bus_v1()Emmanuel Blot1-1/+5
2024-03-21[NFC] target/riscv: refactor `init_registers()`Evgeniy Naydanov3-379/+529
2024-03-07Merge up to 07141132a7d787005c0829618a60b4a842be7847 from upstreamEvgeniy Naydanov1-1/+1
2024-02-27Merge pull request #977 from kr-sc/kr-sc/improve-riscv-controlsEvgeniy Naydanov2-80/+68
2024-02-24src/target/riscv: Help older compilersSevan Janiyan1-1/+1
2024-02-21Merge pull request #1014 from riscv-collab/riscv-batch-cleanupEvgeniy Naydanov5-82/+93
2024-02-16Merge pull request #1016 from tom-van/free-dm-target_listEvgeniy Naydanov1-0/+25
2024-02-15Fixes of review findingsriscv-batch-cleanupJan Matyas1-3/+7
2024-02-13target/riscv: Improve riscv controls that manage the set of available trigger...Kirill Radkin2-80/+68
2024-02-12Merge pull request #1011 from en-sc/en-sc/wa-halt-groupsJan Matyas1-0/+6
2024-02-11target/riscv: free dm and target_list structuresTomas Vanek1-0/+25
2024-02-09Merge pull request #1013 from riscv/dm-calls-cleanupJan Matyas1-10/+11
2024-02-09Merge pull request #1008 from en-sc/en-sc/from_upstreamJan Matyas1-1/+1
2024-02-06riscv/program: Removed dead code for restoring register valuesJan Matyas2-23/+0
2024-02-06Fixes and cleanup in riscv batch and related functionsJan Matyas5-81/+88
2024-02-05Cosmetic cleanup of dm_*() calls in riscv-013.cJan Matyas1-10/+11
2024-02-02target/riscv: set `state` and `debug_reason` in `riscv_halt_go_all_harts()`Evgeniy Naydanov1-0/+6
2024-01-29Merge up to 9659a9b5e28dc615dfb508d301fdd8fa426c191b from upstreamEvgeniy Naydanov1-1/+1
2024-01-28target: get_gdb_arch() accepts target via const pointerEvgeniy Naydanov1-1/+1
2024-01-26Revert "break from long loops on shutdown request"Evgeniy Naydanov4-18/+0
2024-01-25Merge pull request #997 from en-sc/en-sc/priv-accessJan Matyas2-9/+14
2024-01-25Merge pull request #1002 from en-sc/en-sc/arch-stateJan Matyas1-0/+8
2024-01-25Merge pull request #995 from en-sc/en-sc/ctx-fixJan Matyas1-4/+8
2024-01-24target/riscv: report info about target during `poll`Evgeniy Naydanov1-0/+8
2024-01-23target/riscv: move read redirection for `priv` to `riscv-013.c`Evgeniy Naydanov2-9/+14
2024-01-18Merge pull request #992 from en-sc/en-sc/remove-hart-countJan Matyas3-26/+1
2024-01-18Merge pull request #990 from en-sc/en-sc/dmi-definesJan Matyas1-6/+6
2024-01-18Merge pull request #991 from en-sc/en-sc/dm-dmi-address-conversionJan Matyas3-112/+122
2024-01-16target/riscv: cleanup `get_riscv_debug_reg_ctx()`Evgeniy Naydanov1-4/+8
2024-01-16target/riscv: fix addressing in `dm_read`/`dm_wirte`Evgeniy Naydanov3-112/+122
2024-01-16target/riscv: remove `riscv_hart_count()`Evgeniy Naydanov3-26/+1
2024-01-10[NFC] target/riscv: use defined constants in `dmi_*_t` enumsEvgeniy Naydanov1-6/+6
2024-01-09break from long loops on shutdown requestEvgeniy Naydanov4-0/+18
2023-12-22rename dbgbuf to progbufParshintsev Anatoly5-70/+69
2023-12-22introduce execution status for riscv_programParshintsev Anatoly5-80/+140
2023-12-15Clean up clang static analyzer complaints.Tim Newsome2-30/+27
2023-12-11Merge pull request #959 from en-sc/en-sc/progbuf-mem-writeTim Newsome5-146/+273
2023-12-07Update riscv/debug_defines (to sync with riscv-debug-spec:40b9a05)Kirill Radkin5-1297/+850
2023-12-07target/riscv: improve error handling in `write_memory_progbuf()`Evgeniy Naydanov5-146/+273
2023-12-01target/riscv: avoid using VLA in `log_debug_reg()`Evgeniy Naydanov1-1/+6
2023-12-01target/riscv: report helpfull location during register decodeEvgeniy Naydanov1-4/+6
2023-11-17Merge pull request #963 from kr-sc/kr-sc/no-free-triggersTim Newsome1-1/+1
2023-11-16Merge pull request #958 from riscv/set_field_get_fieldTim Newsome5-39/+73
2023-11-16Merge pull request #957 from riscv/sbbusyerrorTim Newsome1-7/+37