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riscv-tools/riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
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us_xds110
vector2
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Author
Files
Lines
2024-03-21
[NFC] target/riscv: refactor `init_registers()`
Evgeniy Naydanov
1
-1
/
+7
2024-02-27
Merge pull request #977 from kr-sc/kr-sc/improve-riscv-controls
Evgeniy Naydanov
1
-3
/
+3
2024-02-13
target/riscv: Improve riscv controls that manage the set of available trigger...
Kirill Radkin
1
-3
/
+3
2024-02-06
Fixes and cleanup in riscv batch and related functions
Jan Matyas
1
-8
/
+8
2024-01-18
Merge pull request #992 from en-sc/en-sc/remove-hart-count
Jan Matyas
1
-6
/
+0
2024-01-16
target/riscv: fix addressing in `dm_read`/`dm_wirte`
Evgeniy Naydanov
1
-2
/
+5
2024-01-16
target/riscv: remove `riscv_hart_count()`
Evgeniy Naydanov
1
-6
/
+0
2023-12-22
rename dbgbuf to progbuf
Parshintsev Anatoly
1
-11
/
+10
2023-12-22
introduce execution status for riscv_program
Parshintsev Anatoly
1
-2
/
+2
2023-11-07
target/riscv: cache requests to trigger configuration
Anastasiya Chernikova
1
-0
/
+6
2023-11-02
target/riscv: Adding register tables to make register names consistent
Anastasiya Chernikova
1
-3
/
+7
2023-10-16
Merge pull request #929 from aap-sc/riscv
Tim Newsome
1
-2
/
+4
2023-10-06
do not assume DTM version unless dtmcontrol is read successfully
Parshintsev Anatoly
1
-2
/
+4
2023-10-02
provide riscv-specific controls to disable triggers from beeing used for watc...
Kirill Radkin
1
-0
/
+4
2023-09-26
openocd does not allow to query status of dcsr.ebreak{u,s,m}
Kirill Radkin
1
-3
/
+4
2023-08-14
target/riscv: Add support for Sv57 translation mode (including second-stage t...
Kirill Radkin
1
-1
/
+1
2023-07-26
target/riscv: support check dbgbase exist
Mark Zhuang
1
-0
/
+1
2023-07-26
target/riscv: add dm layer
Mark Zhuang
1
-6
/
+9
2023-07-18
Merge pull request #878 from en-sc/en-sc/trigg-eq-check
Tim Newsome
1
-0
/
+2
2023-07-17
target/riscv: cleanup trigger setup
Evgeniy Naydanov
1
-0
/
+2
2023-07-14
target/riscv: update some macro
Mark Zhuang
1
-4
/
+3
2023-06-20
target/riscv: Add periodic tick() callback
Tim Newsome
1
-0
/
+4
2023-06-20
target/riscv: Add some event callbacks.
Tim Newsome
1
-0
/
+11
2023-06-20
target/riscv: Remove unused riscv013_on_halt function
Tim Newsome
1
-1
/
+0
2023-06-09
target/riscv: Remove unnecessary prototypes.
Tim Newsome
1
-10
/
+0
2023-05-22
target/riscv: improve register caching (riscv_write_register)
Evgeniy Naydanov
1
-1
/
+9
2023-05-22
target/riscv: use `riscv_reg_t` and `enum gbb_regno` consistently
Evgeniy Naydanov
1
-4
/
+7
2023-04-25
Comment pte_shift
Tim Newsome
1
-0
/
+1
2023-04-25
target/riscv: Add constants for vsatp, hgatp
Tim Newsome
1
-0
/
+2
2023-04-05
Merge pull request #816 from riscv/from_upstream
Tim Newsome
1
-41
/
+17
2023-03-16
Fix build.
Tim Newsome
1
-1
/
+0
2023-03-16
Merge commit '1293ddd65713d6551775b67169387622ada477c1' into from_upstream
Tim Newsome
1
-40
/
+17
2023-03-16
Expose S?aia CSRs if they're on the target.
Tim Newsome
1
-0
/
+3
2023-02-15
target/riscv: hide_csrs configuration option (#787)
Anatoly Parshintsev
1
-0
/
+4
2023-02-10
If XLEN=64 and vsew=64 fails, fall back to vsew=32.
Tim Newsome
1
-0
/
+2
2023-02-08
Move yes_no_maybe_t into riscv.h.
Tim Newsome
1
-0
/
+6
2023-01-04
Merge pull request #777 from riscv/itrigger
Tim Newsome
1
-2
/
+5
2023-01-03
target/riscv: Remove `riscv test_sba_config_reg` command. (#780)
Tim Newsome
1
-3
/
+0
2023-01-02
target/riscv: Add `riscv etrigger` command.
Tim Newsome
1
-0
/
+1
2023-01-02
target/riscv: Add `riscv itrigger` command.
Tim Newsome
1
-2
/
+4
2022-11-23
target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK
Tim Newsome
1
-1
/
+1
2022-11-22
target/riscv: Make poll() use TARGET_UNAVAILABLE.
Tim Newsome
1
-0
/
+4
2022-11-10
target/riscv: Use vlenb to check whether vector registers exist (#762)
Tim Newsome
1
-1
/
+3
2022-11-10
riscv/target: Replace is_halted() with get_hart_state() (#756)
Tim Newsome
1
-2
/
+9
2022-11-09
Use match field for trigger (#725)
Xiang W
1
-0
/
+3
2022-09-30
Remove riscv_info_t.current_hartid
Tim Newsome
1
-9
/
+3
2022-09-13
riscv: don't export local symbols
Antonio Borneo
1
-29
/
+0
2022-08-01
target/riscv: add common magic
Tomas Vanek
1
-0
/
+9
2022-08-01
target/riscv: use struct riscv_info instead of typedef riscv_info_t
Tomas Vanek
1
-6
/
+6
2022-07-02
semihosting: move semihosting_result_t from riscv.h to the semihosting_common.h
Erhan Kurubas
1
-7
/
+3
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