riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-04-03	Support simultaneous resume using hasel (#364)	Tim Newsome	1	-30/+3
2019-01-08	Add comment for reset_delays_wait.	Tim Newsome	1	-13/+4
2018-12-04	Add `riscv reset_delays` for testing.	Tim Newsome	1	-0/+18
2018-11-05	Complete single step before returning. (#319)	Tim Newsome	1	-1/+1
2018-11-02	Fix 0.11 memory leak. (#318)	Tim Newsome	1	-3/+3
2018-08-27	Handle hardware watchpoints hit by RV32 loads and stores (#291)	craigblackmore	1	-1/+1
2018-08-20	From upstream (#286)	Tim Newsome	1	-0/+3
2018-08-06	Fix target not halting when GDB jumps to a hardware breakpoint (#283)	craigblackmore	1	-12/+0
2018-06-12	target/riscv: add semihosting support	Liviu Ionescu	1	-0/+6
2018-04-18	Enforce OpenOCD style guide. (#239)	Tim Newsome	1	-3/+3
2018-04-03	Track misa per-hart even in -rtos mode	Tim Newsome	1	-3/+3
2018-01-23	Fix some niggles found by clang's static analysis.	Tim Newsome	1	-3/+16
2018-01-10	Merge pull request #172 from riscv/dbus_read_comment	Megan Wachs	1	-1/+6
2018-01-08	Propagate register read errors.	Tim Newsome	1	-13/+16
2018-01-05	Merge pull request #173 from riscv/warn_names	Tim Newsome	1	-5/+5
2018-01-04	Make delay update messages debug instead of info.	Tim Newsome	1	-2/+2
2018-01-04	Add a comment in dbus_read	Megan Wachs	1	-1/+6
2018-01-04	Use register names instead of numbers in warnings	Tim Newsome	1	-5/+5
2017-12-27	Get rid of abort() calls.	Tim Newsome	1	-3/+2
2017-12-26	Conform to OpenOCD style guide.	Tim Newsome	1	-265/+271
2017-12-19	WIP xml register for 0.11.	Tim Newsome	1	-145/+49
2017-12-19	Fix register names.	Tim Newsome	1	-1/+1
2017-10-04	Fix compile warnings.	Tim Newsome	1	-2/+2
2017-10-04	Merge pull request #118 from riscv/priv	Tim Newsome	1	-54/+42
2017-10-03	target/riscv: Silence -Werror=return-type	Liviu Ionescu	1	-0/+1
2017-09-30	Make priv readable in 0.11.	Tim Newsome	1	-0/+2
2017-09-30	Share register numbers between 0.11 and 0.13.	Tim Newsome	1	-54/+40
2017-08-15	riscv: Add commands for setting timeouts	Megan Wachs	1	-22/+25
2017-07-12	Share trigger code between 0.11 and 0.13 code.	Tim Newsome	1	-324/+15
2017-07-10	Disable debugger-set triggers on connect	Tim Newsome	1	-62/+74
2017-07-03	Add back support for type 1 triggers.old_triggers	Tim Newsome	1	-42/+120
2017-06-27	Check for errors in read_csr().	Tim Newsome	1	-2/+10
2017-06-13	Fix the build.	Tim Newsome	1	-23/+25
2017-05-22	riscv-v11: Don't perform unexpected operation in cache_write	Megan Wachs	1	-1/+1
2017-04-26	Initialize all registers in examine	Palmer Dabbelt	1	-0/+3
2017-04-26	Add 64-bit and multihart support	Palmer Dabbelt	1	-31/+36
2017-02-07	Update DMI bus width for 0.13.	Tim Newsome	1	-4/+0
2017-02-05	Most gdbserver tests pass now.	Tim Newsome	1	-0/+2605