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2024-03-21[NFC] target/riscv: refactor `init_registers()`Evgeniy Naydanov1-1/+4
The logic in `init_registers()` was quite convoluted. Initialization of each `struct reg` field is separated into function `gdb_regno_<field_name>()`. IMHO, this makes it much easier to reason about the code. Change-Id: Id7faa1464ce026cc5025585d0a6a95a01fb39cee Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
2023-11-02target/riscv: Adding register tables to make register names consistentAnastasiya Chernikova1-1/+1
Added the ability to enter dimensionless registers Change-Id: I1b781959ce4690ec65304142bd9a7c6f540b3e86 Signed-off-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com>
2023-04-25target/riscv: Add constants for vsatp, hgatpTim Newsome1-0/+3
Change-Id: I130a8f7a7abc294bbdf60e7e0ce0bccb72bf920a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-03-16Expose S?aia CSRs if they're on the target.Tim Newsome1-0/+2
Untested, because I don't have a target that implements this. Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a Signed-off-by: Tim Newsome <tim@sifive.com>
2023-01-10target/riscv: added support for missing VCSR registerParshintsev Anatoly1-0/+1
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
2022-11-09Use match field for trigger (#725)Xiang W1-0/+2
* Use match field for trigger The watchpoint cannot capture all data modifications only through the trigger of ANY SIZE and EQUAL, and an error will occur. This patch accommodates watchpoints by adding more types of matches Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> Signed-off-by: Xiang W <wxjstz@126.com> * Update src/target/riscv/riscv.c Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a Signed-off-by: Xiang W <wxjstz@126.com> * Add variable type trigger support Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1 Signed-off-by: Xiang W <wxjstz@126.com> * remove trailing whitespace Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84 Signed-off-by: Xiang W <wxjstz@126.com> * update triggers enumerate Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Xiang W <wxjstz@126.com> Signed-off-by: Tim Newsome <tim@sifive.com> Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
2020-08-24Add SPDX tags for RISC-V files. (#513)Tim Newsome1-0/+2
Requested in http://openocd.zylin.com/#/c/5821/3 Change-Id: I95551a3311d8e128300bacdf463da7ab4edf29a0
2020-08-24Update encoding.h from riscv-opcodes (#514)Tim Newsome1-1/+1
Rename dscratch to dscratch0, since that is what it's called in the spec. Change-Id: Id6271ae272e979cef69e8ef0577b23452fb84f51
2020-02-14Add support for vector register access (#448)Tim Newsome1-0/+18
* WIP Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd * Reading v* registers appears to work. Can't really test it though, because gdb doesn't print them right. Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5 * Total hack to communicate registers to gdb. Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765 * Implement writing vector registers. Fixed reading vector registers. Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214 * Show gdb the actual size of the vector registers. This length may be different per hart. Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493 * Remove outdated todo comment. Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128 * Removed TODO comment. Filed #449 to track this. Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47 * Nicely handle some errors reading/writing V regs. Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
2019-12-10riscv: translate virtual address to physical address. (#425)Hsiangkai1-0/+1
* riscv: translate virtual address to physical address. * riscv: fix formatting errors. * riscv: fix build errors. * riscv: Remove redundant command for virtual address access. * Revert "riscv: Remove redundant command for virtual address access." This reverts commit 990d09eac37d2effcfc5c0d0b5c99678f45e7d7f. * riscv: Change command disable_virt2phys to set_enable_virt2phys 1. Avoid double negative logic to make users easy to use. 2. Add document about new comomand 'riscv set_enable_virt2phys on|off'
2019-09-09Fix flashing HiFive Unleashed (#402)Tim Newsome1-0/+2
* Align algorithm stack to XLEN. This fixes algorithm timeout on RV64 targets. Also improve debug information in various places. Change-Id: Id3121f9c6e753c6a7e14da511e4de0587a6f7b4d * Compile 32-bit RISC-V algorithms for RV32E. Change-Id: I33a698c0c6ba540de29fa0459242c72a67b0cbaa * Remove debug code. Change-Id: I37c966ce0f2d1fe68cd6ae0724d19ae95ebaf51b * Dump start of gdb packets escaping non-printable. Change-Id: Ie5f36b5c9041bfc0e5aa9543f0afe2c4810c2915 * Propagate flash programming errors. Change-Id: I0c938ce7a1062bcc93426538cbc82424000f37b7 * Improve debug messaging. Change-Id: I47ac3518f3b241986c677824864102936100adf6 * Add debug output to flash image. This is helpful when you're debugging the flash algorithm itself, and a nop when running it through OpenOCD. Change-Id: Id44c6498c288872cc2cec79044116ac38198c572 * Make timeout depend on how much data is written. Change-Id: I819efa04cd6f6bd6664afd5c53cc7a8a5c84f54e * Fix issi erase commands. This is required to flash HiFive Unleashed. Change-Id: I33e4869d1d05ca8a1df6136bccf11afda61bfe10 * Fix running algorithm on multicore `-rtos riscv`. The bug was that poll() might change the currently selected hart, and in that case we'd access registers on that other hart after the algorithm is finished. Change-Id: I140431898285cf471b372139cef2378ab4879377 * Make fespi flash algorithm debugging optional. Also add a scheme that allows you to see the stack trace of where a failure occurred if debugging is enabled. Change-Id: Ia9a3a9a941ceba0f8ff6b47da5a8643e5f84b252
2019-07-08RV32E support (#387)Tim Newsome1-0/+1
* In theory support RV32E. Change-Id: Icfe2a40976ae3161f2324e5bb586915aa4c4c7ee * In theory support RV32E. At least very basic tests pass. Change-Id: Ia42e28a3fa020b3e52c92109392c46d009330355 * Fix cut and paste bug. Change-Id: Ibfea68b39d706f59a8c3aa8153bb4db9803958c6 * Add hacks to make RV32E work with gdb. gdb currently requires all 32 GPRs to be present, even on RV32E targets. Once gdb is fixed these hacks can be removed. Change-Id: Idcde648de2ca1a3f5b31315aab35fac86580af2c
2017-12-26Conform to OpenOCD style guide.Tim Newsome1-2/+2
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-19Give FPRs ABI names.Tim Newsome1-1/+33
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19Fix register names.Tim Newsome1-6/+35
Use the ABI ones for every register that we have one for. Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-09-30Share register numbers between 0.11 and 0.13.Tim Newsome1-0/+2
2017-07-27Display register numbers in a more usable format.Tim Newsome1-0/+2
2017-06-15Fix indentation to match OpenOCD style.Tim Newsome1-16/+16
This change is just in the whitespace. There are no code changes. See http://openocd.org/doc-release/doxygen/stylec.html
2017-04-26Add 64-bit and multihart supportPalmer Dabbelt1-0/+28
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This shouldn't have any meaningful effect on the v0.11 support, but it does add generic versions of many functions that will allow me to later refactor the v0.11 support so it's easier to maintain both ports. This started as an emergency feature branch and went on for a long time, so it's all been squashed down into one commit so there isn't a big set of broken commits lying around. The changes are: * You can pass "-rtos riscv" to the target in OpenOCD's configuration file, which enables multi-hart mode. This uses OpenOCD's RTOS support to control all the harts from the debug module using commands like "info threads" in GDB. This support is still expermental. * There is support for RV64I, but due to OpenOCD limitations we only support 32-bit physical addresses. I hope to remedy this by rebasing onto the latest OpenOCD release, which I've heard should fix this. * This matches the latest draft version of the RISC-V debug spec, as of April 26th. This version fixes a number of spec bugs and should be close to the final debug spec.
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