riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-02-10	target: Add 64-bit target address support	Dongxue Zhang	1	-15/+18
2016-12-08	Convert to non-recursive make	Andreas Fritiofson	1	-18/+12
2016-05-24	Make #include guard naming consistent	Marc Schink	4	-13/+12
2016-05-24	Remove FSF address from GPL notices	Marc Schink	9	-3/+25
2015-03-09	openrisc: add profiling function	Franck Jullien	1	-0/+50
2014-11-24	or1k: remove address of the Free Software Foundation	Antony Pavlov	8	-40/+0
2014-10-06	target: constify structures	Spencer Oliver	3	-3/+3
2014-06-22	openrisc: add support for JTAG Serial Port	Franck Jullien	5	-5/+390
2014-06-22	openrisc: restore current JTAG module while polling the CPU	Franck Jullien	1	-1/+10
2014-06-05	target: or1k: remove wrong endian swap from or1k generic code	Franck Jullien	3	-67/+57
2014-04-14	mips32, dsp563xx: fix segfault on Gdb attach	Paul Fertser	1	-1/+1
2014-03-29	target: remove memory leaks	Spencer Oliver	1	-2/+2
2014-01-15	Conform to C99 integer types format specifiers	Hsiangkai Wang	3	-31/+31
2013-12-14	topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc	Sergio Chico	4	-1/+69
2013-10-15	openrisc/tap_vjtag: fix IR setting	Franck Jullien	1	-4/+5
2013-10-15	openrisc/du_adv: check or1k_adv_jtag_init return value	Franck Jullien	1	-21/+49
2013-09-26	Add new target type: OpenRISC	Franck Jullien	8	-0/+3041