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2017-02-10target: Add 64-bit target address supportDongxue Zhang1-5/+5
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-07-19Fix usage of timeval_ms()Andreas Färber1-3/+3
First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-24Remove FSF address from GPL noticesMarc Schink1-3/+1
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson1-4/+4
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2014-02-11arm926ejs: fix write memory operations with caches enabledPaul Fertser1-0/+1
Perform proper ICache flush operations on memory writes. This should fix inability to use software breakpoints for debugging with caches enabled. This patch is only compile-time tested. Commit 1137eaedaf6498f3448cdedf6f93076d9b3fd58a fixed the same issue for arm920t. Among all the arm7_9_common targets only arm926ejs seems to be broken in the same way. Change-Id: I575306ac4319a69fc637b42f7c958f4595c5e81f Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1912 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-10-15arm7_9: Avoid infinite loops in bulk write dispatchingAndreas Fritiofson1-12/+1
Add a mandatory field in struct arm7_9_common for regular, non-optimized memory writes. Together with the existing bulk_memory_write field, this allows variants to select any combination of implementations for regular and bulk writes, without risking infinite loops from accidentally using bulk writes for implementing bulk writes. ARM 7/9 targets may now select arm7_9_memory_write_opt as their target.write_memory implementation, which will dispatch to arm7_9_common.bulk_write_memory if possible, or fallback to arm7_9_common.write_memory otherwise. To avoid loops, bulk write implementations mustn't call any other functions than arm7_9_write_memory_no_opt() to write memory; it will unconditionally call arm7_9_common.write_memory. If they fail, they should simply return error to allow the caller to fallback to regular writes. Tested on a regular ARM7TDMI only. Change-Id: Iae42a6e093e2df68c4823c927d757ae8f42ef388 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1685 Tested-by: jenkins Reviewed-by: Sergey A. Borshch <sb-sf@users.sourceforge.net> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-13[RFC] target: Move bulk_write_memory to arm7_9Andreas Fritiofson1-2/+12
The only remaining user is arm7_9 so remove it from the target API and add it to struct arm7_9_common to support all its variants with minimal changes. Many of the variants are likely not correct in the cache/mmu handling when the bulk write is triggered. This patch does nothing to change that, except for arm946e, where it was easier to do what might be the right thing. Change-Id: Ie73ac07507ff0936fefdb90760046cc8810ed182 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1220 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-06-05update files to correct FSF addressSpencer Oliver1-1/+1
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver1-78/+44
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-23cleanup: rename armv4_5 to arm for readabilitySpencer Oliver1-9/+9
Nothing more than a name change, just to make reading the code a bit simpler. Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/390 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-18cmd: add missing usage varsSpencer Oliver1-0/+2
we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2011-06-04Fix "unused variable" warnings (errors) detected with GCC 4.7.0 - trivial fixesFreddie Chopin1-3/+0
2011-04-01types: write memory now uses constØyvind Harboe1-2/+2
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-19arm: error propagation of arm_jtag_set_instrØyvind Harboe1-4/+12
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-19debug: debug entry error propagationØyvind Harboe1-10/+28
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-19arm: add error propagation for enable/disable mmu cachesØyvind Harboe1-15/+41
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-07-19arm: add error propagation to generic get_ttb fnØyvind Harboe1-2/+4
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-15arm926ejs: -Wshadow warning fixØyvind Harboe1-10/+10
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-06-12TARGET: removed unused parametersAntonio Borneo1-3/+1
Parameters "domain" and "ap" of function armv4_5_mmu_translate_va() are not used. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-06-12TARGET: removed unsed parameterAntonio Borneo1-2/+2
Parameter "type" of function armv4_5_mmu_translate_va() is now not used. Remove the parameter and the "enum" listing its values. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-06-12TARGET: fix handling return code of MMU translationAntonio Borneo1-4/+0
Function armv4_5_mmu_translate_va() now properly signals errors in the return value. Remove former error handling by setting variable "type" to value "-1". Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
2010-06-11arm mmu: error propagation added for address translationØyvind Harboe1-1/+4
The return value for MMU translation was a mess, either error or value. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-21arm breakpoints: amended fix commentØyvind Harboe1-1/+6
the handling of caches, should be moved into the breakpoint specific callbacks rather than being plonked into generic memory write fn's. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-19jtag: retire jtag_get/set_end_state()Øyvind Harboe1-2/+0
Voila! This get rids of mysteries about what what state the TAP is in. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-18jtag: retire one instance of jtag_get_end_state() usageØyvind Harboe1-6/+6
Less global variables.... Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-18jtag: cut down on usage of unintended modification of global end stateØyvind Harboe1-4/+4
jtag_get/set_end_state() is now deprecated. There were lots of places in the code where the end state was unintentionally modified. The big Q is whether there were any places where the intention was to modify the end state. 0.5 is a long way off, so we'll get a fair amount of testing. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-03-08jtag: retire tap fieldØyvind Harboe1-13/+4
jtag_add_dr/ir_scan() now takes the tap as the first argument, rather than for each of the fields passed in. The code never exercised the path where there was more than one tap being scanned, who knows if it even worked. This simplifies the implementation and reduces clutter in the calling code. use jtag_add_ir/dr_plain_scan() for more fancy situations. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-02-21ARM: keep a handle to the PCDavid Brownell1-3/+3
Keep a handle to the PC in "struct arm", and use it. This register is used a fair amount, so this is a net minor code shrink (other than some line length fixes), but mostly it's to make things more readable. For XScale, fix a dodgy sequence while stepping. It was initializing a variable to a non-NULL value, then updating it to handle the step-over-active-breakpoint case, and then later testing for non-NULL to see if it should reverse that step-over-active logic. It should have done like ARM7/ARM9 does: init to NULL. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2010-01-13arm7/9: enable check that DCC downloads have been enabledØyvind Harboe1-0/+1
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2010-01-07misc ARM help/usage updatesDavid Brownell1-1/+1
Usage syntax messages have the same EBNF as the User's Guide; there should be no angle brackets in either place. Uupdate some helptext to be more accurate. Don't use "&function"; functions are like arrays, their address is their name. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: don't clone arm_arch_state() codeDavid Brownell1-8/+2
Have various ARM cores delegate to arm_arch_state() to display basic information, instead of duplicating that logic. This shrinks the code, makes them all report when semihosting is active, and highlights which data are specific to this core. (Like ARM720 not having separate instruction and data caches.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: rename some generic routinesDavid Brownell1-1/+1
Rename some (mostly) generic ARM functions: armv4_5_arch_state() --> arm_arch_state() armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list() armv4_5_init_arch_info() --> arm_init_arch_info() Cores using the microcontroller profile may want a different arch_state() routine though. (Also fix strange indentation in arm_arch_state: use tabs only! And update a call to it, removing assignment-in-conditional.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-07ARM: move opcode macros to <target/arm_opcodes.h>David Brownell1-0/+1
Move the ARM opcode macros from <target/armv4_5.h>, and a few Thumb2 ones from <target/armv7m.h>, to more appropriate homes in a new <target/arm_opcodes.h> file. Removed duplicate opcodes from that v7m/Thumb2 set. Protected a few macro argument references by adding missing parentheses. Tightening up some of the line lengths turned up a curious artifact: the macros for the Thumb opcodes are all 32 bits wide, not 16 bits. There's currently no explanation for why it's done that way... Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-04ARM: rename armv4_5_state_* as arm_state_*David Brownell1-1/+1
And make arm_state_strings[] be const. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-12-03change #include "time_support.h" to <helper/time_support.h>Zachary T Welch1-1/+1
Changes from the flat namespace to heirarchical one. Instead of writing: #include "time_support.h" the following form should be used. #include <helper/time_support.h> The exception is from .c files in the same directory.
2009-12-01target: "mcr" and "mrc" are ARM-specificDavid Brownell1-2/+3
Switch "mrc" and "mcr" commands to be toplevel ARM operations, as they should initially have been. Correct the usage message for both commands: it matches ARM documentation (as one wants!) instead of reordering them to match the funky mrc() and mcr() method usage (sigh). For Cortex-A8: restore a line that got accidentally dropped, so the secure monitor mode shadow registers will show again. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-24remove target_type register_command callbackZachary T Welch1-9/+5
Uses chaining of command_registration structures to eliminate all target_type register_callback routines. Exports the command_handler registration arrays for those target types that are used by others.
2009-11-24arm926ejs: use register_commands()Zachary T Welch1-14/+22
2009-11-24use COMMAND_REGISTER macroZachary T Welch1-2/+2
Replaces direct calls to register_command() with a macro, to allow its parameters to be changed and callers updated in phases.
2009-11-23arm926ejs: retire cp15 commands, handled by mrc/mcr.Øyvind Harboe1-66/+0
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2009-11-22arm926ejs: fix warningsØyvind Harboe1-2/+2
buf_set_u32() operated on an uninitialized stack variable with non-byte boundaries, which led to warnings about reading uninitialized stack. Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
2009-11-22ARM: remove 'armv4_5_common_s' migration #defineDavid Brownell1-2/+2
Finish migrating from the old symbol to the new one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: arm_set_cpsr() handles T and J bitsDavid Brownell1-1/+0
Have arm_set_cpsr() handle the two core state flags, updating the CPU state. This eliminates code in various debug_entry() paths, and marginally improves handling of the J bit. Catch and comment a few holes in the handling of the J bit on ARM926ejs cores ... it's unlikely our users will care about Jazelle mode, but we can at least warn of Impending Doom. If anyone does use it, these breadcrumbs may help them to find the right path through the code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: define two register utilitiesDavid Brownell1-5/+7
Define arm_reg_current() ... returning handle to a given register, and encapsulating the current mode's register shadowing. It's got one current use, for reporting the current register set to GDB. This will let later patches clean up much ARMV4_5_CORE_REG_MODE() nastiness, saving a bit of code. Define and use arm_set_cpsr() ... initially it updates the cached CPSR and sets up state used by arm_reg_current(), plus any SPSR handle. (Later: can also set up for T and J bits.) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-22ARM: simplify CPSR handlingDavid Brownell1-4/+4
Stash a pointer to the CPSR in the "struct arm", to help get rid of the (common) references to its index in the register cache. This removes almost all references to CPSR offsets outside of the toplevel ARM code ... except a pair related to the current ARM11 "simulator" logic (which should be removable soonish). This is a net minor code shrink of a few hundred bytes of object code, and also makes the code more readable. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17ARM: add arm_mode_name()David Brownell1-1/+1
Add and use arm_mode_name() to map from PSR bits to user meaningful names. It uses a new table which, later, can be used to hold other mode-coupled data. Add definitions for the "Secure Monitor" mode, as seen on some ARM11 cores (like ARM1176) and on Cortex-A8. The previous mode name scheme didn't understand that mode. Remove the old mechanism ... there were two copies, caused by Cortex-A8 needing to add "Secure Monitor" mode support. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
2009-11-17command_handler: change 'cmd_ctx' to CMD_CTXZachary T Welch1-11/+11
Convert all command handler 'cmd_ctx' parameter usage with CMD_CTX.
2009-11-17command_handler: change 'args' to CMD_ARGVZachary T Welch1-5/+5
This patch converts all instances of 'args' in COMMAND_HANDLER routines to use CMD_ARGV macro.
2009-11-17command_handler: change to 'argc' to CMD_ARGCZachary T Welch1-2/+2
This patch converts all instances of 'argc' in COMMAND_HANDLER routines to use CMD_ARGC.
2009-11-17ARM9TDMI: remove now-needless "struct arm9tdmi"David Brownell1-6/+4
And move the rest of the vector_catch stuff into the C file; it's not part of the module interface. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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