| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2006-11-22 | - added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. ↵ | drath | 1 | -0/+49 | |
| configuration - added support for loading .bit files into Xilinx Virtex-II devices - added support for the Gateworks GW16012 JTAG dongle - merged CFI fixes from XScale branch - a few minor fixes git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60 | |||||
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index : riscv-tools/riscv-openocd.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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