aboutsummaryrefslogtreecommitdiff
path: root/src/flash
AgeCommit message (Collapse)AuthorFilesLines
2017-06-13Fix the build.Tim Newsome1-6/+6
Main change is to make riscv_addr_t be unsigned. The rest is mechanical fixing of types, print statements, and a few signed/unsigned compares. Smoketest indicates everything is working more or less as before.
2017-06-13Merge branch 'remotes/openocd/master' into riscv64Tim Newsome32-638/+2005
Merged 1025be363e2bf42f1613083223a2322cc3a9bd4c Conflicts: src/flash/nor/Makefile.am src/rtos/Makefile.am src/rtos/rtos.c src/target/Makefile.am src/target/target.c src/target/target_type.h Doesn't build yet, but I fixed the conflicts that git pointed out.
2017-06-02flash: nor: ath79: fix build failure due to recent MIPS changesPaul Fertser1-37/+35
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4151 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
2017-05-31flash: Add support for Atheros (ath79) SPI interfaceTobias Diedrich3-0/+906
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-08stm32l4: support flashing L45x/46x devicesJuha Niskanen1-7/+18
Also fixes incorrect comment about MSI range. Change-Id: If1339a00e50db44195dfcd5c767ba3f5d9035451 Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-on: http://openocd.zylin.com/4122 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo1-31/+31
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-26Correct an off-by-one in argument parsingPalmer Dabbelt1-1/+1
2017-04-26riscv: Fix some blocking compile warningsMegan Wachs1-3/+5
2017-04-26fespi: Allow the ctrl_base address specified as a parameterMegan Wachs1-14/+25
2017-04-26Add 64-bit and multihart supportPalmer Dabbelt1-15/+21
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This shouldn't have any meaningful effect on the v0.11 support, but it does add generic versions of many functions that will allow me to later refactor the v0.11 support so it's easier to maintain both ports. This started as an emergency feature branch and went on for a long time, so it's all been squashed down into one commit so there isn't a big set of broken commits lying around. The changes are: * You can pass "-rtos riscv" to the target in OpenOCD's configuration file, which enables multi-hart mode. This uses OpenOCD's RTOS support to control all the harts from the debug module using commands like "info threads" in GDB. This support is still expermental. * There is support for RV64I, but due to OpenOCD limitations we only support 32-bit physical addresses. I hope to remedy this by rebasing onto the latest OpenOCD release, which I've heard should fix this. * This matches the latest draft version of the RISC-V debug spec, as of April 26th. This version fixes a number of spec bugs and should be close to the final debug spec.
2017-04-25stm32l4: support flashing L496 devicesJuha Niskanen1-1/+6
Change-Id: I3effc5b675c853433170391c5eaf46edc067b6e7 Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-on: http://openocd.zylin.com/4108 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24mips32, pic32 use uint8_t in 8 bit scan functionSalvador Arroyo1-2/+1
Makes code shorter. Change-Id: I6cc01adffbea063ccb071ddf3a3e3d81727b29ce Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4004 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24Added 512K flashing support for em3587Byron Kubert1-0/+5
The Silicon Labs EM3587 and EM3588 may have 512K of flash. This fix allows for 512K to be specifiied on the command line when flashing a device. Change-Id: I18cc4bd0d14e1f2069066734a7396bcccf3de941 Signed-off-by: Byron Kubert <byronk@google.com> Reviewed-on: http://openocd.zylin.com/3795 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24flash/nor/tcl: Make verify_bank parameter optionalMarc Schink1-6/+15
Make the 'offset' parameter optional, if omitted simply start at the beginning of the flash bank. Additionally, check if the argument is out of bounds of the flash bank. Change-Id: Id1959eee5c395666c35f26342c3c50134dd564e5 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3858 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-04-24flash/nor/tcl: Fix some format specifiersMarc Schink1-10/+9
Change-Id: I2255aede9713cb7ef538d7433dd900d8da7a51ad Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3857 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24stm32lx: fix dual-bank configuration for Cat.5 and Cat.6 devicesCezaryGapinski1-50/+69
Default values for .first_bank_size_kb and .has_dual_banks fields described in stm32lx_parts[] do not fully describe the real device memory layouts. Basing on: STM32L0x1 RM0377 STM32L0x2 RM0376 STM32L0x3 RM0367 STM32Lxxxx RM0038 correct values for memory layouts were selected: id = 0x447 STM32L0xx (Cat.5) <- dual bank flash for size 192 or 128 KBytes, single bank for 64 KBytes id = 0x436 STM32L1xx (Cat.4 / Cat.3 - Medium + / High Density) <- only one size of the bank, default values are correct id = 0x437 STM32L1xx (Cat.5 / Cat.6) <- always dual bank, but size of the bank can be different For that reason .part_info field in struct stm32lx_flash_bank is a dynamic field with fields copied from stm32lx_parts[] and overwriten to correct values for specific chips and memory sizes. Change-Id: If638cb0a9916097bfd4eda77d64feaf1ef2d2147 Signed-off-by: Cezary Gapiński <cezary.gapinski@gmail.com> Reviewed-on: http://openocd.zylin.com/4074 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-04-24Fix flash writing on stm32l0Armin van der Togt1-14/+2
Fix "couldn't use loader, falling back to page memory writes" error on stm32l0 which was caused by the use of cortex-m3 instructions in the flash loader code. The loader is rewritten using cortex-m0 compatible instructions Signed-off-by: Armin van der Togt <armin@otheruse.nl> Change-Id: If23027b8e09f74e45129e1f8452a04bb994c424e Reviewed-on: http://openocd.zylin.com/4036 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24flash/nor/at91samd: fix chip erase of a secured deviceTomas Vanek1-4/+10
'at91samd chip-erase' command did not work on secured device. Fix it changing address of DSU.CTRL register (see Atmel SAM D21 datasheet, 13.9. Intellectual Property Protection). While on it check error return of DSU.CTRL write. Change-Id: I83155a634a5458cdc0cc16c99c0e155eb1d8b3d6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reported-by: Thomas Irmen <tirmen@gmx.net> Reviewed-on: http://openocd.zylin.com/4043 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-24Add support for the ATMEL SAM G55 Xplained Pro board and CPU.Jerome Lambourg1-0/+70
Change-Id: Iffe59dcf9f2cb1f5949c37d11fe0d2141a47f8da Signed-off-by: Paul Fertser <fercerpav@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3922 Tested-by: jenkins Reviewed-by: Leo Zhang <liang.zhang@microchip.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-23nrf51: Add new HWID 0x008FDamyan Mitev1-0/+7
Add new entry in nrf51_known_devices_table for nRF51822 chip found on chinese Core51822 dev board. The chp has markings N51822 / QFAAH1 / 1630FW Nordic Semiconductor nRF51 Series Compatibility matrix confirms that this chip has 256K Flash and 16K RAM. Change-Id: I571d15913c6f6e02a6f09c883d7dfc5a66b57c28 Signed-off-by: Damyan Mitev <damyan_mitev@mail.bg> Reviewed-on: http://openocd.zylin.com/4091 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-04-23flash Kinetis: reduce a flash write message severity to infoJoakim Nohlgård1-1/+1
There is nothing the user can do if their device does not support sector programming, there is no reason to have this message at warning level. Change-Id: Ic9b7386e59b64fece7fbfdc543bdfeeed3eae73d Signed-off-by: Joakim Nohlgård <joakim.nohlgard@eistec.se> Reviewed-on: http://openocd.zylin.com/4105 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2017-04-10fespi: Reset may have occurred. Need to set TXWM again. There are probably ↵Megan Wachs1-12/+24
more places that need this added.
2017-03-29nrf51: Remove pointer castAndreas Fritiofson1-3/+4
Int may not be 32 bit long. Change-Id: I420f7efeb484eb35c1d7c20e1575b0b31ed8c9ff Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3930 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-03-23Revert "(WIP) Force algorithms to 64 bit"Palmer Dabbelt1-2/+2
This reverts commit 466b7b48816e0b80c84ab55e01e9f58676c89687.
2017-03-23(WIP) Force algorithms to 64 bitPalmer Dabbelt1-2/+2
2017-03-23some devicePalmer Dabbelt1-0/+1
2017-02-13flash/nor: avrf: support atmega128rfa1Karl Palsson1-0/+1
Tested with a Dresden Elektronik deRFmega128 module. Change-Id: I91da3b11b60e78755360b08453ed368d6d396651 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/2790 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang5-5/+5
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-01-15flash/nor: fix doc/help and range test for flash protectTomas Vanek2-7/+15
Commit 77a1c01ccbb1150ffe749a7373cf6c4dc15ecad0 introduced infrastructure for utilizing protection blocks of different size than erase sector. Parts of doc/help kept reading 'sector' instead of 'protection block'. flash_driver_protect() parameter range testing did not switched to bank->num_prot_blocks. This change fixes it. Change-Id: Iec301761190a1a1bcc4cb005a519b9e5e4fede51 Reported-by: Mark Odell <mark@odell.ws> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3917 Tested-by: jenkins Reviewed-by: Mark Odell <mrfirmware@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-23Correct off by 1 in malloc, which causes this to fail on macOS (and in ↵mwachs51-1/+1
theory on any platform).
2016-12-18riscv: Increase the number of Algorithm StepsMegan Wachs1-1/+1
2016-12-08Convert to non-recursive makeAndreas Fritiofson3-126/+110
Change-Id: I11f8bc8553957e2ff083c09e72e16881e4d3bb6f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3865 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08flash/nor/efm32: Support flash size smaller than 32kkevin1-3/+3
The current implementation fails on devices with less than 32k of flash (such as several devices in the Zero Gecko family) because the 'assert' assumes (incorrectly) that the number of flash banks will always be >= 32. This change ensures that at least one word of lock bits is always read in order to support devices with less than 32k of flash. Signed-off-by: Kevlar Harness <software@klystron.com> Change-Id: I59febe2cb690c893a5057a5f72918e146cf2afe4 Reviewed-on: http://openocd.zylin.com/3806 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08at91sam4: Add missing SAM4S family CHIPIDs and remove FWS=6.Owen Kirby1-17/+275
Add missing CHIPID values for all SAM4S parts listed in revision K of Atmel-11100-32-bit Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf. I have also removed the FWS=6 workaround, as this appears to be a copy-paste error from the SAM3X family. Change-Id: I1ce1d82911f39d6fcb8f04034f5c9c9bf2818466 Signed-off-by: Owen Kirby <oskirby@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3837 Tested-by: jenkins
2016-12-08at91sam4: Add flash description and chipid for SAM4Cxx variants.Owen Kirby1-4/+195
Chip ID and flash layout taken from Atmel-11102F-ATARM-SAM4C32-SAM4C16-SAM4C8-SAM4C4-Datasheet_27-Mar-15 and tested on a SAM4C32-EK (rev A). Change-Id: I68aae5b60994c0b5964ea9031d40bc76ba025675 Signed-off-by: Owen Kirby <oskirby@gmail.com> Reviewed-on: http://openocd.zylin.com/3527 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-12-08xmc4xxx: Add support for XMC4300Andreas Färber1-2/+10
XMC4300 can reuse the existing XMC4700/XMC4800 sectors support. Add support for XMC4300 AA to the info command. Change-Id: Id929a51d20c73bd869a4457ffedc48ad5fa3f2df Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3875 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08flash/nor: at91samd protection bits write fixTomas Vanek2-40/+44
Flash protection set on a device with MANW=1 was lost after reset. Since #2903 the driver honored MANW bit and issued Write Page command just for main flash write. This change adds similar technique to samd_modify_user_row(). Minor code improvements: samd_check_error() returns error code corresponding to error type instead of bool. samd_check_error() does not clear STATUS register if no error bit is set. Eliminated double error check in call sequence samd_issue_nvmctrl_command() folowed by samd_check_error(). Missing error code ERROR_FLASH_PROTECTED added to src/flash/common.h. Change-Id: Icf59ab8803305d0cb3170c8a5089b8f9828b99f8 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3550 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-11-30Use portable format specifier for size_tAlbert Ou1-1/+1
This fixes a gcc warning [-Werror=format] on an i686-pc-linux-gnu host, which defines size_t as unsigned int instead of long int.
2016-11-27Don't write SCKDIV when flashingMegan Wachs1-4/+0
The target may have already configured its clock to run at a higher frequency and would have set SCKDIV and other dividers at that time. Don't restore the SCKDIV to its default or the flash interface may run too fast and programming will fail. Otherwise, the default value is fine and there is no need to write SCKDIV.
2016-11-27Add timeout to infinite loop.Tim Newsome1-1/+13
Change-Id: I7d005b4779154b4dfe8c9a26f4f0e351f426df9b
2016-11-25Add some timeouts that I ran into.Tim Newsome1-11/+48
Change-Id: I8eeb1c934ceead0d99dcdc618a3f8aa351119cb0
2016-11-23Fix typo.Tim Newsome1-1/+1
Change-Id: If04ba1103817f772fe55659cb3b5b4533c734f2a
2016-11-19Merge branch 'sifive/add_issi_flash' into riscvTim Newsome1-1/+1
2016-11-19Fix off-by-one error in assert.Tim Newsome1-1/+1
Change-Id: I86447c747a212175be560170378c655ac801f5a6
2016-11-19Add the ISSI SPI Flash to the listMegan Wachs1-1/+1
2016-11-18Flash at 8KB/s, using 10,000 byte working area.Tim Newsome1-67/+168
If the working area is large enough, every fespi_write() results in just a single algorithm execution. Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
2016-11-172KB/s, by using the algorithm more.Tim Newsome1-7/+42
Change-Id: If55dcf432f9243355ed22eb8d1559ecdbca3c5c9
2016-11-17Base work for using a much smarter algorithm.Tim Newsome1-52/+203
Change-Id: I0bf6af12ac2e3c07ffe3f95ad490eb4a88244a97
2016-11-17Merge branch 'Og' into enable_flash_progTim Newsome3-8/+8
2016-11-16Use algorithm to speed up fespi flash programming.Tim Newsome1-377/+500
It's still really slow, at 854b/s, but it seems to work and it's a lot of new code. Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
generated by cgit v1.1 at 2024-10-12 21:04:27 +0000