riscv-tools/riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-02-17	Fix access FPU registers again.	Tim Newsome	1	-46/+80
2017-02-17	Fix use of REG vs CSR constants.	Tim Newsome	1	-26/+30
2017-02-17	Bunch of register access refactoring.	Tim Newsome	2	-546/+161
2017-02-16	Check busy before triggering another command.	Tim Newsome	1	-46/+50
2017-02-15	Check for errors after read/write.	Tim Newsome	1	-4/+12
2017-02-15	Fix double read, which might have side effects.	Tim Newsome	1	-4/+6
2017-02-15	Make MemTest32 pass.	Tim Newsome	1	-2/+2
2017-02-15	Some memory access works.	Tim Newsome	2	-351/+161
2017-02-14	Merge pull request #15 from sifive/get_set_reg_error	Tim Newsome	2	-9/+45
2017-02-14	Make general CSR reads work.	Tim Newsome	1	-36/+22
2017-02-14	Make it all the way through examine().	Tim Newsome	1	-220/+85
2017-02-14	More dbus->dmi.	Tim Newsome	1	-21/+65
2017-02-13	Read misa during examine(), using program buffer.	Tim Newsome	2	-100/+939
2017-02-13	dbus -> dmi	Tim Newsome	2	-160/+160
2017-02-13	Discover XLEN using abstract reg reads.	Tim Newsome	2	-42/+64
2017-02-10	Attempt to discover XLEN with abstract reg reads	Tim Newsome	4	-108/+118
2017-02-10	riscv: Add register name to message when they do not exist.	Megan Wachs	2	-7/+7
2017-02-10	Halt target in riscv_examine().	Tim Newsome	2	-30/+45
2017-02-09	Add debug_defines.h.	Tim Newsome	1	-0/+630
2017-02-08	Detect and smoketest data and ibuf registers.	Tim Newsome	1	-28/+69
2017-02-08	Correctly parse dmcontrol.	Tim Newsome	1	-51/+29
2017-02-07	Update DMI bus width for 0.13.	Tim Newsome	2	-10/+2
2017-02-07	Merge remote-tracking branch 'origin/riscv' into HEAD	Megan Wachs	7	-2297/+6016
2017-02-06	Merge pull request #16 from sifive/0.13	Tim Newsome	6	-2297/+5375
2017-02-05	Add missing header file.	Tim Newsome	1	-0/+62
2017-02-05	Use the set/reg register error return code when registers don't exist.	Megan Wachs	2	-9/+45
2017-02-05	Add the first difference for 0.13 targets.	Tim Newsome	1	-1/+1
2017-02-05	Use the csrNNN name instead of "mstatus".	Tim Newsome	1	-2/+6
2017-02-05	Most gdbserver tests pass now.	Tim Newsome	5	-2296/+5308
2017-01-26	Merge pull request #13 from sifive/disable_interrupts	Tim Newsome	1	-0/+18
2017-01-25	riscv: disable interrupts for all priviledge levels	Megan Wachs	1	-3/+2
2017-01-25	riscv: Use proper UINT packing and unpacking routines for disabling interrupt...	Megan Wachs	1	-5/+12
2017-01-25	riscv: Globally disable interrupts when running algorithms.	Megan Wachs	1	-0/+12
2016-12-24	Merge pull request #11 from sifive/malloc_off_by_1	Tim Newsome	1	-1/+1
2016-12-23	Correct off by 1 in malloc, which causes this to fail on macOS (and in theory...	mwachs5	1	-1/+1
2016-12-19	Merge pull request #9 from sifive/increase_as_size	Tim Newsome	1	-1/+1
2016-12-18	riscv: Increase the number of Algorithm Steps	Megan Wachs	1	-1/+1
2016-12-08	Merge pull request #7 from sifive/temp_verify_blank_check	Tim Newsome	1	-0/+30
2016-12-07	riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just...	Megan Wachs	1	-0/+30
2016-12-01	Fix issue #6: build failure on gcc 6	Tim Newsome	1	-1/+1
2016-11-30	Merge pull request #5 from sifive/format-warning	Tim Newsome	1	-1/+1
2016-11-30	Use portable format specifier for size_t	Albert Ou	1	-1/+1
2016-11-30	Merge pull request #4 from sifive/mwachs5-patch-sckdiv	Megan Wachs	1	-4/+0
2016-11-27	Don't write SCKDIV when flashing	Megan Wachs	1	-4/+0
2016-11-27	Add timeout to infinite loop.	Tim Newsome	1	-1/+13
2016-11-25	Add some timeouts that I ran into.	Tim Newsome	1	-11/+48
2016-11-25	Cope better if the target unexpectedly resets.	Tim Newsome	1	-4/+11
2016-11-23	Fix typo.	Tim Newsome	1	-1/+1
2016-11-19	Merge branch 'sifive/add_issi_flash' into riscv	Tim Newsome	1	-1/+1
2016-11-19	Fix off-by-one error in assert.	Tim Newsome	1	-1/+1