aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2017-06-14Merge pull request #62 from riscv/riscv64Palmer Dabbelt308-10671/+17226
Merge mainline OpenOCD
2017-06-13Fix the build.Tim Newsome5-77/+85
Main change is to make riscv_addr_t be unsigned. The rest is mechanical fixing of types, print statements, and a few signed/unsigned compares. Smoketest indicates everything is working more or less as before.
2017-06-13Merge branch 'remotes/openocd/master' into riscv64Tim Newsome303-10594/+17141
Merged 1025be363e2bf42f1613083223a2322cc3a9bd4c Conflicts: src/flash/nor/Makefile.am src/rtos/Makefile.am src/rtos/rtos.c src/target/Makefile.am src/target/target.c src/target/target_type.h Doesn't build yet, but I fixed the conflicts that git pointed out.
2017-06-08Merge pull request #60 from riscv/timTim Newsome1-25/+25
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08Fix dmi_read() indentation; remove \n in LOG_ERRORTim Newsome1-25/+25
2017-06-07riscv: Move the initialization of the field inside the structure for consistencyMegan Wachs1-5/+1
2017-06-07riscv: v13 -- dmi_write must still check for the OP resultv20170608Megan Wachs1-21/+17
2017-06-06%p already includes 0x (on gcc)Tim Newsome1-4/+4
2017-06-06Don't leave fd undefined.Tim Newsome1-1/+1
When gcc isn't optimizing well, it might not realize that it's not possible to return fd without initializing it, and then the build fails due to -Werror.
2017-06-02flash: nor: ath79: fix build failure due to recent MIPS changesPaul Fertser1-37/+35
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4151 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
2017-05-31flash: Add support for Atheros (ath79) SPI interfaceTobias Diedrich6-1/+948
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31imx_gpio: add mmap based jtag interface for IMX processorsGrzegorz Kostka6-2/+623
For some targets (like nrf51) sysfs driver is too slow. This patch implements memory maped driver for IMX processors. Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should work on any NXP IMX CPU. Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7 Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com> Reviewed-on: http://openocd.zylin.com/4106 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-25Return 5 (SIGBREAK) not 2 (SIGINT) after a stepPalmer Dabbelt1-1/+1
GDB seems to just go off the rails if I return a SIGINT.
2017-05-25Pass EVENT_RESUMED in the RTOSPalmer Dabbelt1-2/+3
I missed this event. It appears to do nothing.
2017-05-25Invalidate the register cache when rtos_hartid==-1Palmer Dabbelt1-1/+4
This means I don't know what hart to look at, so I might as well invalidate the register cache. Without this, you might get stale registers the first time you ask for them.
2017-05-25Invalidate the register cache on step, resume, resetPalmer Dabbelt2-0/+14
I thought OpenOCD did this, but it looks like that doesn't happen when runningi in RTOS mode. With this I can get to the end of most of the RTOS tests, but they SIGINT instead of exiting.
2017-05-25Merge pull request #52 from riscv/v11_read_without_intMegan Wachs1-1/+1
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-22riscv-v11: Don't perform unexpected operation in cache_writeMegan Wachs1-1/+1
2017-05-15Check for abstractcs.busy, not just CMDERR_BUSYPalmer Dabbelt1-0/+4
This fixes a race condition when reading/writing memory.
2017-05-15Go back to 32-word read/write buffersPalmer Dabbelt1-2/+2
The larger buffers are really slow on Spike.
2017-05-15Don't re-read registers after they're writtenPalmer Dabbelt1-8/+0
This was just a sanity check.
2017-05-15Print out the actual CSR that's readPalmer Dabbelt1-0/+1
2017-05-15Build fixesPalmer Dabbelt2-3/+3
2017-05-15riscv: Remove some compile warningsMegan Wachs1-2/+0
2017-05-12jtag/drivers: Add Cypress KitProg driverForest Crossman7-1/+1058
This patch adds a driver for the SWD-only Cypress KitProg programmer/debugger. Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5 Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3221 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-05-11Shim back in some old interfaces for nowPalmer Dabbelt1-16/+72
2017-05-09tcl/cpld: add config file for Altera 5M570Z CPLD (MAXV family)Moritz Fischer1-0/+6
Change-Id: I229c746be27b7c4fa01f48a6ed54ab2679b50ab1 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/4109 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-09Allow all harts to be resetPalmer Dabbelt3-39/+112
2017-05-08stm32l4: support flashing L45x/46x devicesJuha Niskanen2-8/+19
Also fixes incorrect comment about MSI range. Change-Id: If1339a00e50db44195dfcd5c767ba3f5d9035451 Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-on: http://openocd.zylin.com/4122 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, use scan32 function for reading impcode/idcode.Salvador Arroyo3-60/+19
There is no need to implement scan code in functions mips_ejtag_get_idcode/impcode(), use mips_ejtag_drscan_32(). Impcode/idcode saved in ejtag.info. Reorder the code in the callers of this functions. Change-Id: Ia829c783a0b24c6a65cade736113fa6f67b0a170 Signed-off-by: Salvador Arroyo <salvador@telecable.es> Reviewed-on: http://openocd.zylin.com/4003 Tested-by: jenkins Reviewed-by: Peter Mamonov <pmamonov@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips breakpoints supportSalvador Arroyo1-46/+105
Breakpoint setting based on length (kind) only. Added 16bit aligned 32bit software breakpoints support and same filtering before setting breakpoint. Set the required isa bit in hardware breakpoints. Drop the isa bit in software breakpoints. Change-Id: I7020f27be16015194b76f385d9b8e5af496d0dfc Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4124 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32: add micromips isa handlingSalvador Arroyo5-19/+91
Read and save configuration registers, up to 4. Config3 holds the micromips implementation info. Added isa implementation info to mips32_common. Added isa filter to avoid common mistakes, but only if one isa mode is implemented. When resuming the isa requested is set if more than one isa mode is implemented. Change-Id: I1d6526c5525bffac8d75e031b842b2edc6310e28 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4123 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, convert miniprograms with code definitionSalvador Arroyo1-44/+63
Needed to run in micromips mode. Seems that if an isa is supported in debug mode it also supported in kernel mode. The contrary is not true. Change-Id: I1feb8e2c376f4db97089f05c20bc0cd177208fb3 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4033 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add support for micromips in debug modeSalvador Arroyo8-270/+374
Micromips is 16bit oriented, branch and jumps are 16 bit based. The upper half 16bits of a 32bit instruction with the major opcode, must go first in the instruction stream, hence the SWAP16 macro and swap16 array function, needed if the code is written as 32 bit word in little endian cores. Endianess info added to ejtag_iinfo. Pointer to ejtag_info and isa field added to pracc context. MIPS32 code are renamed to MIPS32_ISA_... To select the isa, the new code has an additional isa parameter (1 for micromips, 0 for mips32). In JR instruction the isa bit must be set to execute micromips code. The suffix u is added to the OP codes to avoid signed/unsigned comparison errors and to make sure the right shift is performed logically. The isa in debug mode is updated in the poll function. Code for miniprograms, in kernel mode, need to be converted. CFI code only for mips32. Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4032 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add microMips instruction subsetSalvador Arroyo1-0/+95
Only reencoded MIPS32 instructions. Added some instructions for crc code. Micromips isa in debug mode is only needed for pic32mm cores. Pic32mz seems that only works with MIPS32 isa when in debug mode. Change-Id: I07059e153a7000ea9204f20b6b37edf6a7623455 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4022 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add option to avoid check in last instructionSalvador Arroyo3-33/+36
This option is needed, for example, when exiting debug mode in bmips targets. The last instruction is a NOP, not a DERET. When working in async mode this check is not done, mips32_pracc_queue_exec() pass the parameter to mips32_pracc_exec() and never use it. Change-Id: I4c7ed4feb1588b62e2645b955b501b6671113b36 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4021 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, add realloc codeSalvador Arroyo3-44/+35
If max_code is reached realloc memory. If fails to realloc the error is propagated and every call to pracc_add() returns immediately. The exec function logs the error. Change-Id: Idd4ed9d9b8b19b7d6842d0bc5ebb05f943726705 Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4020 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-08mips32, change in pracc_list for dynamic allocationSalvador Arroyo3-44/+45
pracc_list points to an array with code in the lower half and addr in the upper half. Change it to a struct with an instruction field and an address field. Requiered to make reallocation easier. As a side effect the code is less quirky. Change-Id: Ibf904a33a2f35a7f69284d2a2114f4b4ae79219f Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es> Reviewed-on: http://openocd.zylin.com/4019 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2017-05-05 Avoid accessing null target->reg_cacheMegan Wachs1-0/+6
GDB might request registers even if target was not successfully initialized.
2017-05-05Merge pull request #43 from riscv/read-from-0Megan Wachs1-4/+4
Read from 0
2017-05-02Fix compile failure on MacOSXMatthias Welwarsky2-7/+3
MacOSX tool chain defines __unused in "sys/cdefs.h", causing a collision. Remove the local define to avoid polluting the compilers internal symbol namespace. Change-Id: I16370c4518e6aeec482dd689e7db80628f846ee3 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4118 Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2017-05-01riscv-013: more consistent parensMegan Wachs1-2/+2
2017-05-01riscv-013: Correct sign extension of address on read_memory for lower bits ↵Megan Wachs1-1/+1
as well
2017-05-01riscv-013: Correct sign extension of address on read_memoryMegan Wachs1-2/+2
2017-05-01Correct debugging print in read_memoryMegan Wachs1-1/+1
2017-05-01Fix an assertion when reading from 0Palmer Dabbelt1-1/+1
2017-05-01Correct previous hart caching logicPalmer Dabbelt1-1/+2
2017-04-27Clean up unused read_memory codePalmer Dabbelt1-31/+0
2017-04-26Correct an off-by-one in argument parsingPalmer Dabbelt1-1/+1
2017-04-26Keep calling the old poll on v0.11 targetsPalmer Dabbelt1-2/+11
This is another thing that should be fixed correctly. Essentially this just uses the old codepath, which works for v0.11.
generated by cgit v1.1 at 2024-08-05 01:50:04 +0000