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2017-12-15Use %ll instead of %L instead of scanf.macbuildTim Newsome1-1/+1
Mac build barfs on L, and the manpage says they're equivalent. Hopefully fixes #147 Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-11Merge pull request #143 from riscv/fmvTim Newsome1-2/+2
Fix build.
2017-12-11Fix build.Tim Newsome1-2/+2
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11Merge pull request #131 from riscv/small_progbufTim Newsome7-1018/+780
Support program buffers that are just 2 instructions large
2017-11-27Merge pull request #140 from riscv/encodingTim Newsome2-58/+216
Update encoding.h.
2017-11-27Update encoding.h.Tim Newsome2-58/+216
Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
2017-11-16Add missing return.Tim Newsome1-0/+1
Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-14Merge pull request #127 from riscv/jtag_debugTim Newsome1-62/+10
Clean up this JTAG debug code.
2017-11-03Merge pull request #133 from riscv/no-russianPalmer Dabbelt2-0/+0
No Russian
2017-11-01Merge branch 'riscv' into small_progbufTim Newsome3-6/+2
Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01Merge pull request #134 from riscv/compileTim Newsome1-1/+1
Fix compile warning with gcc 6.3.0
2017-11-01Merge pull request #135 from riscv/fuller_buildTim Newsome1-1/+1
Build OpenOCD the way we expect users to build it.
2017-10-31Build OpenOCD the way we expect users to build it.Tim Newsome1-1/+1
Change-Id: I3769137bc3109b44da76f2ca689d351bb93e7832
2017-10-27Fix compile warning with new gcc.Tim Newsome1-1/+1
Change-Id: I14ebf597f41429c0fc3ebac8da9c9f62c78fb1ae
2017-10-27Support 64-bit FPRs on RV32.Tim Newsome3-34/+328
Because there is no instruction that moves just half of a 64-bit FPR to/from a GPR, we need to use scratch memory for this operation. This code can theoretically use: 1. DMI_DATA, if it is memory mapped in the target. 2. DMI_PROGBUF, if it is writable in the target. 3. A user-configured address. I have only tested this code very lightly. One reason is that gdb thinks that on RV32 harts every register is 32 bits wide. Another is that this is mostly proof-of-concept to satisfy the small program buffer code review, which I don't want to drag out forever. Existing tests don't realize that floating support was broken with RV32D, and don't realize that it still doesn't work because of the gdb problem mentioned above. This change improves Issue #110 but there's more work to be done. Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-26No RussianPalmer Dabbelt2-0/+0
2017-10-26Merge pull request #132 from riscv/cleanupTim Newsome1-4/+0
Remove unused variables.
2017-10-25Remove unused variables.Tim Newsome1-4/+0
Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-24Remove more unused functionality.Tim Newsome1-6/+0
Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24Add a fence after memory writes.Tim Newsome1-7/+16
Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24Remove more unused code.Tim Newsome1-6/+0
Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24Remove more unused code.Tim Newsome1-48/+6
Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-23Remove unused functionality.Tim Newsome2-268/+0
Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
2017-10-23Properly fix memory read when encountering busy.Tim Newsome1-36/+101
Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-18Pay attention to impebreak.Tim Newsome4-64/+95
This required updating debug_defines.h, which caused a few other small cleanups as well. Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18Remove unused functionality.Tim Newsome2-73/+3
Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
2017-10-18Still restore registers if an access failed.Tim Newsome1-8/+11
Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
2017-10-18Fix FPR access.Tim Newsome1-5/+8
Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
2017-10-17Don't crash when encountering RV64.Tim Newsome1-7/+3
Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
2017-10-17Memory read/write works if the core can keep up.Tim Newsome1-11/+8
Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
2017-10-17MemTest64 passes.Tim Newsome2-4/+18
Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-16Memtest{16,32} pass.Tim Newsome4-217/+126
Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-13At least some memory writes work.Tim Newsome3-130/+94
Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-12Register read/write might be working.Tim Newsome2-72/+67
Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12WIP; doesn't work.Tim Newsome5-174/+55
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-10Remove duplicate progbuf size variable.Tim Newsome1-21/+13
Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-09Merge pull request #123 from riscv/fast_rbbTim Newsome3-33/+147
Add read buffer to bitbang, improving performance.
2017-10-09Merge pull request #129 from riscv/minor_revertTim Newsome1-1/+1
Revert this LOG_INFO to LOG_DEBUG.
2017-10-08Revert this LOG_INFO to LOG_DEBUG.Tim Newsome1-1/+1
Change-Id: I75dd7667a542aa1c6ea10f97fe1e00dd1ecba69d
2017-10-06Clean up this JTAG debug code.Tim Newsome1-62/+10
Change-Id: Ie7c773b98271d11085d5e50c40b64990710de387
2017-10-04Merge pull request #126 from riscv/compileTim Newsome1-2/+2
Fix compile warnings.
2017-10-04Fix compile warnings.Tim Newsome1-2/+2
Partly fixes #124. Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
2017-10-04Merge pull request #125 from riscv/cleanupTim Newsome1-35/+0
Revert ae74097f (extra ftdi debug).
2017-10-04Revert ae74097f (extra ftdi debug).Tim Newsome1-35/+0
Instead it makes more sense to push the debug changes to jtag/core.c. Change-Id: I73bafa2a054e1f72b7752cfbce9ffc14303fc4c4
2017-10-04Ensure the buffer doesn't overflow.Tim Newsome3-19/+46
Tested with a variety of prime buffer sizes. Change-Id: I2b4835d46adf4c971111da88e8de4b46eb8dad41
2017-10-04Merge pull request #118 from riscv/privTim Newsome3-57/+47
Fix priv access
2017-10-03Add read buffer to bitbang, improving performance.Tim Newsome3-24/+111
This reduces the time for one testcase where OpenOCD connects to a simulator from 12.30s to 5.35s! Running all our tests went from 13m13s to 3m55s. Change-Id: I7dc774e1e0f5752905ac4318fd9b85b930374a05
2017-10-03Merge pull request #116 from riscv/multigdbTim Newsome3-13/+39
Fix trigger code to work with multi-gdb mode instead of RTOS mode
2017-10-03Merge pull request #120 from gnu-mcu-eclipse/riscv-warningsTim Newsome3-1/+8
Silence some clang warnings
2017-10-03Merge pull request #121 from gnu-mcu-eclipse/riscv-reorderTim Newsome1-1/+1
flash/nor/Makefile.am: keep files in lexicographical order
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