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2017-06-22Ignore build directorygitignore-buildColin Schmidt1-0/+1
the riscv-tools build script make a subdirectory to build in, other submodules ignore this file
2017-06-20Merge pull request #68 from riscv/multicorePalmer Dabbelt4-38/+89
Testsuite now passes on multicore target
2017-06-20Set hardware triggers on all harts.multicoreTim Newsome1-33/+69
Right now we're using "threads" to represent harts. gdb/OpenOCD assume there's only one set of hardware breakpoints among all threads. Make it so.
2017-06-20Don't immediately segfault with -rtos on v0.11.Tim Newsome1-0/+3
2017-06-20Comment curious code.Tim Newsome1-0/+4
2017-06-20Update list of "threads" when harts are discovered.Tim Newsome3-5/+13
This ensures that "info threads" is accurate as soon as gdb connects. Also print out number of triggers that is discovered in examine().
2017-06-20Merge pull request #67 from riscv/cosmeticsTim Newsome3-77/+147
Various cosmetic improvements
2017-06-19Put early DEBUG notice of XLEN back.Tim Newsome1-0/+5
2017-06-16Update debug_defines. Clarify debug output.Tim Newsome2-52/+118
Update debug_defines from the spec, commit 920ec9a690. Decode dmstatus scans in the debug output.
2017-06-16Fix comment.Tim Newsome1-1/+1
2017-06-16Tell the user about detected harts.Tim Newsome1-8/+10
2017-06-16Tighten up debug output.Tim Newsome1-17/+14
Assuming the program allocating code works, we don't need its output. Only output parts of the debug RAM that are actually doing something.
2017-06-16Merge pull request #66 from riscv/whitespaceTim Newsome6-335/+333
Fix indentation to match OpenOCD style.
2017-06-15Fix indentation to match OpenOCD style.Tim Newsome6-335/+333
This change is just in the whitespace. There are no code changes. See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15Merge pull request #64 from riscv/release-fixesTim Newsome2-5/+12
Two fixes from the release branch
2017-06-15Merge pull request #65 from riscv/print64Palmer Dabbelt1-4/+7
Fix print statements to work with 64-bit addresses
2017-06-15Fix print statements to work with 64-bit addressesTim Newsome1-4/+7
2017-06-15Jump to the RTOS hartid after haltingPalmer Dabbelt1-0/+7
When I disappeared the polls everywhere I forgot to sanitize the hartid after halting. This is an invariant that GDB expects: when you return from a halt whatever thread is marked as currently selected is the thread that the next register accesses reference.
2017-06-15Clear abstract errors from register_read_directPalmer Dabbelt1-5/+5
2017-06-15Merge pull request #63 from riscv/crc64Palmer Dabbelt1-1/+1
Accept 64-bit addresses in CRC requests.
2017-06-15Accept 64-bit addresses in CRC requests.Tim Newsome1-1/+1
2017-06-14Merge pull request #62 from riscv/riscv64Palmer Dabbelt308-10671/+17226
Merge mainline OpenOCD
2017-06-13Fix the build.Tim Newsome5-77/+85
Main change is to make riscv_addr_t be unsigned. The rest is mechanical fixing of types, print statements, and a few signed/unsigned compares. Smoketest indicates everything is working more or less as before.
2017-06-13Merge branch 'remotes/openocd/master' into riscv64Tim Newsome303-10594/+17141
Merged 1025be363e2bf42f1613083223a2322cc3a9bd4c Conflicts: src/flash/nor/Makefile.am src/rtos/Makefile.am src/rtos/rtos.c src/target/Makefile.am src/target/target.c src/target/target_type.h Doesn't build yet, but I fixed the conflicts that git pointed out.
2017-06-08Merge pull request #60 from riscv/timTim Newsome1-25/+25
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08Fix dmi_read() indentation; remove \n in LOG_ERRORTim Newsome1-25/+25
2017-06-07riscv: Move the initialization of the field inside the structure for consistencyMegan Wachs1-5/+1
2017-06-07riscv: v13 -- dmi_write must still check for the OP resultv20170608Megan Wachs1-21/+17
2017-06-06%p already includes 0x (on gcc)Tim Newsome1-4/+4
2017-06-06Don't leave fd undefined.Tim Newsome1-1/+1
When gcc isn't optimizing well, it might not realize that it's not possible to return fd without initializing it, and then the build fails due to -Werror.
2017-06-02flash: nor: ath79: fix build failure due to recent MIPS changesPaul Fertser1-37/+35
Change-Id: I7139b0658f048afea2d16216c93e8946356a630d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4151 Tested-by: jenkins Reviewed-by: Salvador Arroyo <sarroyofdez@yahoo.es>
2017-05-31flash: Add support for Atheros (ath79) SPI interfaceTobias Diedrich6-1/+948
Supported SoCs: AR71xx, AR724x, AR91xx, AR93xx, QCA9558 Extended and revised version of my original patch submitted by Dmytro here: http://openocd.zylin.com/#/c/3390 This driver is using pure SPI mode, so the flash base address is not used except some flash commands (e.g. "flash program") need it to distinguish the banks. Example config with all 3 chip selects: flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0 flash bank flash1 ath79 0x10000000 0 0 0 $_TARGETNAME cs1 flash bank flash2 ath79 0x20000000 0 0 0 $_TARGETNAME cs2 Example usage: > flash probe flash0 Found flash device 'win w25q128fv' (ID 0x001840ef) flash 'ath79' found at 0x00000000 > flash probe flash1 No SPI flash found > flash probe flash2 No SPI flash found > flash banks > flash read_bank flash0 /tmp/test.bin 0x00000000 0x1000 reading 4096 bytes from flash @0x00000000 wrote 4096 bytes to file /tmp/test.bin from flash bank 0 at offset 0x00000000 in 28.688066s (0.139 KiB/s) Change-Id: I5feb697722c07e83a9c1b361a9db7b06bc699aa8 Signed-off-by: Tobias Diedrich <ranma+openocd@tdiedrich.de> Reviewed-on: http://openocd.zylin.com/3612 Tested-by: jenkins Reviewed-by: Dmytro <dioptimizer@hotmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-31imx_gpio: add mmap based jtag interface for IMX processorsGrzegorz Kostka6-2/+623
For some targets (like nrf51) sysfs driver is too slow. This patch implements memory maped driver for IMX processors. Mostly based on bcm2835gpio. Tested on imx6ul CPU. However, it should work on any NXP IMX CPU. Change-Id: Idace4c98181c6e9c64dd158bfa52631204b5c4a7 Signed-off-by: Grzegorz Kostka <kostka.grzegorz@gmail.com> Reviewed-on: http://openocd.zylin.com/4106 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-25Return 5 (SIGBREAK) not 2 (SIGINT) after a stepPalmer Dabbelt1-1/+1
GDB seems to just go off the rails if I return a SIGINT.
2017-05-25Pass EVENT_RESUMED in the RTOSPalmer Dabbelt1-2/+3
I missed this event. It appears to do nothing.
2017-05-25Invalidate the register cache when rtos_hartid==-1Palmer Dabbelt1-1/+4
This means I don't know what hart to look at, so I might as well invalidate the register cache. Without this, you might get stale registers the first time you ask for them.
2017-05-25Invalidate the register cache on step, resume, resetPalmer Dabbelt2-0/+14
I thought OpenOCD did this, but it looks like that doesn't happen when runningi in RTOS mode. With this I can get to the end of most of the RTOS tests, but they SIGINT instead of exiting.
2017-05-25Merge pull request #52 from riscv/v11_read_without_intMegan Wachs1-1/+1
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-22riscv-v11: Don't perform unexpected operation in cache_writeMegan Wachs1-1/+1
2017-05-15Check for abstractcs.busy, not just CMDERR_BUSYPalmer Dabbelt1-0/+4
This fixes a race condition when reading/writing memory.
2017-05-15Go back to 32-word read/write buffersPalmer Dabbelt1-2/+2
The larger buffers are really slow on Spike.
2017-05-15Don't re-read registers after they're writtenPalmer Dabbelt1-8/+0
This was just a sanity check.
2017-05-15Print out the actual CSR that's readPalmer Dabbelt1-0/+1
2017-05-15Build fixesPalmer Dabbelt2-3/+3
2017-05-15riscv: Remove some compile warningsMegan Wachs1-2/+0
2017-05-12jtag/drivers: Add Cypress KitProg driverForest Crossman7-1/+1058
This patch adds a driver for the SWD-only Cypress KitProg programmer/debugger. Change-Id: I3a9a8011a762781d560ebb305597e782a4f9a8e5 Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3221 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2017-05-11Shim back in some old interfaces for nowPalmer Dabbelt1-16/+72
2017-05-09tcl/cpld: add config file for Altera 5M570Z CPLD (MAXV family)Moritz Fischer1-0/+6
Change-Id: I229c746be27b7c4fa01f48a6ed54ab2679b50ab1 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/4109 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-05-09Allow all harts to be resetPalmer Dabbelt3-39/+112
2017-05-08stm32l4: support flashing L45x/46x devicesJuha Niskanen2-8/+19
Also fixes incorrect comment about MSI range. Change-Id: If1339a00e50db44195dfcd5c767ba3f5d9035451 Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com> Reviewed-on: http://openocd.zylin.com/4122 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
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