aboutsummaryrefslogtreecommitdiff
path: root/tcl/board/vd_xt8_jtag.cfg
diff options
context:
space:
mode:
Diffstat (limited to 'tcl/board/vd_xt8_jtag.cfg')
-rw-r--r--tcl/board/vd_xt8_jtag.cfg28
1 files changed, 28 insertions, 0 deletions
diff --git a/tcl/board/vd_xt8_jtag.cfg b/tcl/board/vd_xt8_jtag.cfg
new file mode 100644
index 0000000..867b9e7
--- /dev/null
+++ b/tcl/board/vd_xt8_jtag.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# Xtensa xt8 through JTAG
+
+source [find interface/vdebug.cfg]
+
+set CHIPNAME xt8
+set CPUTAPID 0x120034e5
+
+# vdebug select transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+# BFM hierarchical path and input clk period
+vdebug bfm_path Testbench.u_vd_jtag_bfm 10ns
+
+# DMA Memories to access backdoor, the values come from generated xtensa-core-xt8.cfg
+#vdebug mem_path Testbench.Xtsubsystem.Core0.iram0.iram0.mem.dataArray 0x40000000 0x100000
+#vdebug mem_path Testbench.Xtsubsystem.Core0.dram0.dram0.mem.dataArray 0x3ff00000 0x40000
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config"
+source [find target/xtensa-core-xt8.cfg]