diff options
Diffstat (limited to 'src/target/cortex_a.c')
-rw-r--r-- | src/target/cortex_a.c | 139 |
1 files changed, 59 insertions, 80 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 6eb6aa9..b3a8a41 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -55,6 +55,7 @@ #include "target_type.h" #include "arm_opcodes.h" #include "arm_semihosting.h" +#include "jtag/interface.h" #include "transport/transport.h" #include "smp.h" #include <helper/time_support.h> @@ -70,6 +71,8 @@ static int cortex_a_set_hybrid_breakpoint(struct target *target, struct breakpoint *breakpoint); static int cortex_a_unset_breakpoint(struct target *target, struct breakpoint *breakpoint); +static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, + uint32_t value, uint32_t *dscr); static int cortex_a_mmu(struct target *target, int *enabled); static int cortex_a_mmu_modify(struct target *target, int enable); static int cortex_a_virt2phys(struct target *target, @@ -250,21 +253,21 @@ static int cortex_a_wait_instrcmpl(struct target *target, uint32_t *dscr, bool f * Writes final value of DSCR into *dscr. Pass force to force always * reading DSCR at least once. */ struct armv7a_common *armv7a = target_to_armv7a(target); - int64_t then = timeval_ms(); - while ((*dscr & DSCR_INSTR_COMP) == 0 || force) { - force = false; - int retval = mem_ap_read_atomic_u32(armv7a->debug_ap, + int retval; + + if (force) { + retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr); if (retval != ERROR_OK) { LOG_ERROR("Could not read DSCR register"); return retval; } - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for InstrCompl=1"); - return ERROR_FAIL; - } } - return ERROR_OK; + + retval = cortex_a_wait_dscr_bits(target, DSCR_INSTR_COMP, DSCR_INSTR_COMP, dscr); + if (retval != ERROR_OK) + LOG_ERROR("Error waiting for InstrCompl=1"); + return retval; } /* To reduce needless round-trips, pass in a pointer to the current @@ -293,19 +296,12 @@ static int cortex_a_exec_opcode(struct target *target, if (retval != ERROR_OK) return retval; - int64_t then = timeval_ms(); - do { - retval = mem_ap_read_atomic_u32(armv7a->debug_ap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) { - LOG_ERROR("Could not read DSCR register"); - return retval; - } - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for cortex_a_exec_opcode"); - return ERROR_FAIL; - } - } while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */ + /* Wait for InstrCompl bit to be set */ + retval = cortex_a_wait_instrcmpl(target, &dscr, true); + if (retval != ERROR_OK) { + LOG_ERROR("Error waiting for cortex_a_exec_opcode"); + return retval; + } if (dscr_p) *dscr_p = dscr; @@ -359,17 +355,11 @@ static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data, dscr = *dscr_p; /* Wait for DTRRXfull */ - int64_t then = timeval_ms(); - while ((dscr & DSCR_DTR_TX_FULL) == 0) { - retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap, - a->armv7a_common.debug_base + CPUDBG_DSCR, - &dscr); - if (retval != ERROR_OK) - return retval; - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for read dcc"); - return ERROR_FAIL; - } + retval = cortex_a_wait_dscr_bits(a->armv7a_common.arm.target, + DSCR_DTR_TX_FULL, DSCR_DTR_TX_FULL, &dscr); + if (retval != ERROR_OK) { + LOG_ERROR("Error waiting for read dcc"); + return retval; } retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap, @@ -391,19 +381,10 @@ static int cortex_a_dpm_prepare(struct arm_dpm *dpm) int retval; /* set up invariant: INSTR_COMP is set after ever DPM operation */ - int64_t then = timeval_ms(); - for (;; ) { - retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap, - a->armv7a_common.debug_base + CPUDBG_DSCR, - &dscr); - if (retval != ERROR_OK) - return retval; - if ((dscr & DSCR_INSTR_COMP) != 0) - break; - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for dpm prepare"); - return ERROR_FAIL; - } + retval = cortex_a_wait_instrcmpl(dpm->arm->target, &dscr, true); + if (retval != ERROR_OK) { + LOG_ERROR("Error waiting for dpm prepare"); + return retval; } /* this "should never happen" ... */ @@ -752,7 +733,7 @@ static int cortex_a_poll(struct target *target) static int cortex_a_halt(struct target *target) { - int retval = ERROR_OK; + int retval; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); @@ -765,18 +746,12 @@ static int cortex_a_halt(struct target *target) if (retval != ERROR_OK) return retval; - int64_t then = timeval_ms(); - for (;; ) { - retval = mem_ap_read_atomic_u32(armv7a->debug_ap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - return retval; - if ((dscr & DSCR_CORE_HALTED) != 0) - break; - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for halt"); - return ERROR_FAIL; - } + dscr = 0; /* force read of dscr */ + retval = cortex_a_wait_dscr_bits(target, DSCR_CORE_HALTED, + DSCR_CORE_HALTED, &dscr); + if (retval != ERROR_OK) { + LOG_ERROR("Error waiting for halt"); + return retval; } target->debug_reason = DBG_REASON_DBGRQ; @@ -915,18 +890,12 @@ static int cortex_a_internal_restart(struct target *target) if (retval != ERROR_OK) return retval; - int64_t then = timeval_ms(); - for (;; ) { - retval = mem_ap_read_atomic_u32(armv7a->debug_ap, - armv7a->debug_base + CPUDBG_DSCR, &dscr); - if (retval != ERROR_OK) - return retval; - if ((dscr & DSCR_CORE_RESTARTED) != 0) - break; - if (timeval_ms() > then + 1000) { - LOG_ERROR("Timeout waiting for resume"); - return ERROR_FAIL; - } + dscr = 0; /* force read of dscr */ + retval = cortex_a_wait_dscr_bits(target, DSCR_CORE_RESTARTED, + DSCR_CORE_RESTARTED, &dscr); + if (retval != ERROR_OK) { + LOG_ERROR("Error waiting for resume"); + return retval; } target->debug_reason = DBG_REASON_NOTHALTED; @@ -1206,6 +1175,8 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre retval = cortex_a_poll(target); if (retval != ERROR_OK) return retval; + if (target->state == TARGET_HALTED) + break; if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for target halt"); return ERROR_FAIL; @@ -1689,7 +1660,7 @@ static int cortex_a_assert_reset(struct target *target) */ if (transport_is_swd() || (target->reset_halt && (jtag_get_reset_config() & RESET_SRST_NO_GATING))) - jtag_add_reset(0, 1); + adapter_assert_reset(); } else { LOG_ERROR("%s: how to reset?", target_name(target)); @@ -1712,7 +1683,7 @@ static int cortex_a_deassert_reset(struct target *target) LOG_DEBUG(" "); /* be certain SRST is off */ - jtag_add_reset(0, 0); + adapter_deassert_reset(); if (target_was_examined(target)) { retval = cortex_a_poll(target); @@ -1763,14 +1734,22 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, { /* Waits until the specified bit(s) of DSCR take on a specified value. */ struct armv7a_common *armv7a = target_to_armv7a(target); - int64_t then = timeval_ms(); + int64_t then; int retval; - while ((*dscr & mask) != value) { + if ((*dscr & mask) == value) + return ERROR_OK; + + then = timeval_ms(); + while (1) { retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("Could not read DSCR register"); return retval; + } + if ((*dscr & mask) == value) + break; if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for DSCR bit change"); return ERROR_FAIL; @@ -2944,7 +2923,7 @@ static int cortex_a_virt2phys(struct target *target, if (retval != ERROR_OK) return retval; return armv7a_mmu_translate_va_pa(target, (uint32_t)virt, - (uint32_t *)phys, 1); + phys, 1); } COMMAND_HANDLER(cortex_a_handle_cache_info_command) @@ -2952,7 +2931,7 @@ COMMAND_HANDLER(cortex_a_handle_cache_info_command) struct target *target = get_current_target(CMD_CTX); struct armv7a_common *armv7a = target_to_armv7a(target); - return armv7a_handle_cache_info_command(CMD_CTX, + return armv7a_handle_cache_info_command(CMD, &armv7a->armv7a_mmu.armv7a_cache); } @@ -2991,7 +2970,7 @@ COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command) } n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_a->isrmasking_mode); - command_print(CMD_CTX, "cortex_a interrupt mask %s", n->name); + command_print(CMD, "cortex_a interrupt mask %s", n->name); return ERROR_OK; } @@ -3017,7 +2996,7 @@ COMMAND_HANDLER(handle_cortex_a_dacrfixup_command) } n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode); - command_print(CMD_CTX, "cortex_a domain access control fixup %s", n->name); + command_print(CMD, "cortex_a domain access control fixup %s", n->name); return ERROR_OK; } |