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Diffstat (limited to 'src/target/arm_adi_v5.h')
-rw-r--r--src/target/arm_adi_v5.h40
1 files changed, 40 insertions, 0 deletions
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 6e2d8a1..17365bd 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -158,6 +158,15 @@
#define DP_APSEL_MAX (255)
#define DP_APSEL_INVALID (-1)
+/* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
+enum swd_special_seq {
+ LINE_RESET,
+ JTAG_TO_SWD,
+ SWD_TO_JTAG,
+ SWD_TO_DORMANT,
+ DORMANT_TO_SWD,
+};
+
/**
* This represents an ARM Debug Interface (v5) Access Port (AP).
* Most common is a MEM-AP, for memory access.
@@ -234,6 +243,12 @@ struct adiv5_dap {
/* dap transaction list for WAIT support */
struct list_head cmd_journal;
+ /* pool for dap_cmd objects */
+ struct list_head cmd_pool;
+
+ /* number of dap_cmd objects in the pool */
+ size_t cmd_pool_size;
+
struct jtag_tap *tap;
/* Control config */
uint32_t dp_ctrl_stat;
@@ -265,6 +280,12 @@ struct adiv5_dap {
bool ti_be_32_quirks;
/**
+ * STLINK adapter need to know if last AP operation was read or write, and
+ * in case of write has to flush it with a dummy read from DP_RDBUFF
+ */
+ bool stlink_flush_ap_write;
+
+ /**
* Signals that an attempt to reestablish communication afresh
* should be performed before the next access.
*/
@@ -285,6 +306,10 @@ struct adiv5_dap {
struct dap_ops {
/** connect operation for SWD */
int (*connect)(struct adiv5_dap *dap);
+
+ /** send a sequence to the DAP */
+ int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
+
/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
uint32_t *data);
@@ -333,6 +358,21 @@ enum ap_type {
};
/**
+ * Send an adi-v5 sequence to the DAP.
+ *
+ * @param dap The DAP used for reading.
+ * @param seq The sequence to send.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_send_sequence(struct adiv5_dap *dap,
+ enum swd_special_seq seq)
+{
+ assert(dap->ops != NULL);
+ return dap->ops->send_sequence(dap, seq);
+}
+
+/**
* Queue a DP register read.
* Note that not all DP registers are readable; also, that JTAG and SWD
* have slight differences in DP register support.