diff options
Diffstat (limited to 'contrib/loaders')
-rw-r--r-- | contrib/loaders/Makefile | 3 | ||||
-rw-r--r-- | contrib/loaders/debug/xscale/Makefile | 33 | ||||
-rw-r--r-- | contrib/loaders/debug/xscale/debug_handler.S | 716 | ||||
-rw-r--r-- | contrib/loaders/debug/xscale/debug_handler.inc | 101 | ||||
-rw-r--r-- | contrib/loaders/debug/xscale/debug_handler.ld | 49 | ||||
-rw-r--r-- | contrib/loaders/debug/xscale/protocol.h | 68 | ||||
-rwxr-xr-x | contrib/loaders/flash/fpga/xilinx_bscan_spi.py | 314 | ||||
-rw-r--r-- | contrib/loaders/flash/kinetis/Makefile | 19 | ||||
-rw-r--r-- | contrib/loaders/flash/kinetis/kinetis_flash.inc | 6 | ||||
-rw-r--r-- | contrib/loaders/flash/kinetis/kinetis_flash.s | 101 | ||||
-rw-r--r-- | contrib/loaders/flash/stm32lx.S | 32 |
11 files changed, 1232 insertions, 210 deletions
diff --git a/contrib/loaders/Makefile b/contrib/loaders/Makefile index 2e5eba8..31cccb5 100644 --- a/contrib/loaders/Makefile +++ b/contrib/loaders/Makefile @@ -12,7 +12,8 @@ ARM_CROSS_COMPILE ?= arm-none-eabi- arm_dirs = \ flash/fm4 \ flash/kinetis_ke \ - flash/xmc1xxx + flash/xmc1xxx \ + debug/xscale arm: for d in $(common_dirs); do \ diff --git a/contrib/loaders/debug/xscale/Makefile b/contrib/loaders/debug/xscale/Makefile new file mode 100644 index 0000000..a0455c7 --- /dev/null +++ b/contrib/loaders/debug/xscale/Makefile @@ -0,0 +1,33 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- + +CC=$(CROSS_COMPILE)gcc +OBJCOPY=$(CROSS_COMPILE)objcopy +OBJDUMP=$(CROSS_COMPILE)objdump + +CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL +LDFLAGS = -Tdebug_handler.ld + +all: debug_handler.inc + +.PHONY: clean + +.INTERMEDIATE: debug_handler.elf + +debug_handler.elf: protocol.h + +%.elf: %.S + $(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ + +%.lst: %.elf + $(OBJDUMP) -S $< > $@ + +%.bin: %.elf + $(OBJCOPY) -Obinary $< $@ + +%.inc: %.bin + $(BIN2C) < $< > $@ + +clean: + -rm -f *.elf *.lst *.bin *.inc diff --git a/contrib/loaders/debug/xscale/debug_handler.S b/contrib/loaders/debug/xscale/debug_handler.S new file mode 100644 index 0000000..66dfa88 --- /dev/null +++ b/contrib/loaders/debug/xscale/debug_handler.S @@ -0,0 +1,716 @@ +/*************************************************************************** + * Copyright (C) 2006 by Dominic Rath * + * Dominic.Rath@gmx.de * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * + ***************************************************************************/ +#include "protocol.h" + + .text + .align 4 + +@ Disable thumb mode + .code 32 + +@ send word to debugger +.macro m_send_to_debugger reg +1: + mrc p14, 0, r15, c14, c0, 0 + bvs 1b + mcr p14, 0, \reg, c8, c0, 0 +.endm + +@ receive word from debugger +.macro m_receive_from_debugger reg +1: + mrc p14, 0, r15, c14, c0, 0 + bpl 1b + mrc p14, 0, \reg, c9, c0, 0 +.endm + +@ save register on debugger, small +.macro m_small_save_reg reg + mov r0, \reg + bl send_to_debugger +.endm + +@ save status register on debugger, small +.macro m_small_save_psr + mrs r0, spsr + bl send_to_debugger +.endm + +@ wait for all outstanding coprocessor accesses to complete +.macro m_cpwait + mrc p15, 0, r0, c2, c0, 0 + mov r0, r0 + sub pc, pc, #4 +.endm + +.global reset_handler +.global undef_handler +.global swi_handler +.global prefetch_abort_handler +.global data_abort_handler +.global irq_handler +.global fiq_handler + +.section .part1 , "ax" + +reset_handler: + @ read DCSR + mrc p14, 0, r13, c10, c0 + @ check if global enable bit (GE) is set + ands r13, r13, #0x80000000 + + bne debug_handler + + @ set global enable bit (GE) + mov r13, #0xc0000000 + mcr p14, 0, r13, c10, c0 + +debug_handler: + + @ save r0 without modifying other registers + m_send_to_debugger r0 + + @ save lr (program PC) without branching (use macro) + m_send_to_debugger r14 + + @ save non-banked registers and spsr (program CPSR) + m_small_save_reg r1 + m_small_save_reg r2 + m_small_save_reg r3 + m_small_save_reg r4 + m_small_save_reg r5 + m_small_save_reg r6 + m_small_save_reg r7 + m_small_save_psr + + mrs r0, spsr + + @ prepare program PSR for debug use (clear Thumb, set I/F to disable interrupts) + bic r0, r0, #PSR_T + orr r0, r0, #(PSR_I | PSR_F) + + @ examine mode bits + and r1, r0, #MODE_MASK + cmp r1, #MODE_USR + + bne not_user_mode + + @ replace USR mode with SYS + bic r0, r0, #MODE_MASK + orr r0, r0, #MODE_SYS + +not_user_mode: + + b save_banked_registers + +@ command loop +@ wait for command from debugger, than execute desired function +get_command: + bl receive_from_debugger + + @ 0x0n - register access + cmp r0, #0x0 + beq get_banked_registers + + cmp r0, #0x1 + beq set_banked_registers + + @ 0x1n - read memory + cmp r0, #0x11 + beq read_byte + + cmp r0, #0x12 + beq read_half_word + + cmp r0, #0x14 + beq read_word + + @ 0x2n - write memory + cmp r0, #0x21 + beq write_byte + + cmp r0, #0x22 + beq write_half_word + + cmp r0, #0x24 + beq write_word + + @ 0x3n - program execution + cmp r0, #0x30 + beq resume + + cmp r0, #0x31 + beq resume_w_trace + + @ 0x4n - coprocessor access + cmp r0, #0x40 + beq read_cp_reg + + cmp r0, #0x41 + beq write_cp_reg + + @ 0x5n - cache and mmu functions + cmp r0, #0x50 + beq clean_d_cache + + cmp r0, #0x51 + beq invalidate_d_cache + + cmp r0, #0x52 + beq invalidate_i_cache + + cmp r0, #0x53 + beq cpwait + + @ 0x6n - misc functions + cmp r0, #0x60 + beq clear_sa + + cmp r0, #0x61 + beq read_trace_buffer + + cmp r0, #0x62 + beq clean_trace_buffer + + @ return (back to get_command) + b get_command + +@ ---- + +@ resume program execution +resume: + @ restore CPSR (SPSR_dbg) + bl receive_from_debugger + msr spsr, r0 + + @ restore registers (r7 - r0) + bl receive_from_debugger @ r7 + mov r7, r0 + bl receive_from_debugger @ r6 + mov r6, r0 + bl receive_from_debugger @ r5 + mov r5, r0 + bl receive_from_debugger @ r4 + mov r4, r0 + bl receive_from_debugger @ r3 + mov r3, r0 + bl receive_from_debugger @ r2 + mov r2, r0 + bl receive_from_debugger @ r1 + mov r1, r0 + bl receive_from_debugger @ r0 + + @ resume addresss + m_receive_from_debugger lr + + @ branch back to application code, restoring CPSR + subs pc, lr, #0 + +@ get banked registers +@ receive mode bits from host, then run into save_banked_registers to + +get_banked_registers: + bl receive_from_debugger + +@ save banked registers +@ r0[4:0]: desired mode bits +save_banked_registers: + @ backup CPSR + mrs r7, cpsr + msr cpsr_c, r0 + nop + + @ keep current mode bits in r1 for later use + and r1, r0, #MODE_MASK + + @ backup banked registers + m_send_to_debugger r8 + m_send_to_debugger r9 + m_send_to_debugger r10 + m_send_to_debugger r11 + m_send_to_debugger r12 + m_send_to_debugger r13 + m_send_to_debugger r14 + + @ if not in SYS mode (or USR, which we replaced with SYS before) + cmp r1, #MODE_SYS + + beq no_spsr_to_save + + @ backup SPSR + mrs r0, spsr + m_send_to_debugger r0 + +no_spsr_to_save: + + @ restore CPSR for SDS + msr cpsr_c, r7 + nop + + @ return + b get_command + +@ ---- + + +@ set banked registers +@ receive mode bits from host, then run into save_banked_registers to + +set_banked_registers: + bl receive_from_debugger + +@ restore banked registers +@ r0[4:0]: desired mode bits +restore_banked_registers: + @ backup CPSR + mrs r7, cpsr + msr cpsr_c, r0 + nop + + @ keep current mode bits in r1 for later use + and r1, r0, #MODE_MASK + + @ set banked registers + m_receive_from_debugger r8 + m_receive_from_debugger r9 + m_receive_from_debugger r10 + m_receive_from_debugger r11 + m_receive_from_debugger r12 + m_receive_from_debugger r13 + m_receive_from_debugger r14 + + @ if not in SYS mode (or USR, which we replaced with SYS before) + cmp r1, #MODE_SYS + + beq no_spsr_to_restore + + @ set SPSR + m_receive_from_debugger r0 + msr spsr, r0 + +no_spsr_to_restore: + + @ restore CPSR for SDS + msr cpsr_c, r7 + nop + + @ return + b get_command + +@ ---- + +read_byte: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +rb_loop: + ldrb r0, [r2], #1 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + bl send_to_debugger + + subs r1, r1, #1 + bne rb_loop + + @ return + b get_command + +@ ---- + +read_half_word: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +rh_loop: + ldrh r0, [r2], #2 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + bl send_to_debugger + + subs r1, r1, #1 + bne rh_loop + + @ return + b get_command + +@ ---- + +read_word: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +rw_loop: + ldr r0, [r2], #4 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + bl send_to_debugger + + subs r1, r1, #1 + bne rw_loop + + @ return + b get_command + +@ ---- + +write_byte: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +wb_loop: + bl receive_from_debugger + strb r0, [r2], #1 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + subs r1, r1, #1 + bne wb_loop + + @ return + b get_command + +@ ---- + +write_half_word: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +wh_loop: + bl receive_from_debugger + strh r0, [r2], #2 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + subs r1, r1, #1 + bne wh_loop + + @ return + b get_command + +@ ---- + +write_word: + @ r2: address + bl receive_from_debugger + mov r2, r0 + + @ r1: count + bl receive_from_debugger + mov r1, r0 + +ww_loop: + bl receive_from_debugger + str r0, [r2], #4 + + @ drain write- (and fill-) buffer to work around XScale errata + mcr p15, 0, r8, c7, c10, 4 + + subs r1, r1, #1 + bne ww_loop + + @ return + b get_command + +@ ---- + +clear_sa: + @ read DCSR + mrc p14, 0, r0, c10, c0 + + @ clear SA bit + bic r0, r0, #0x20 + + @ write DCSR + mcr p14, 0, r0, c10, c0 + + @ return + b get_command + +@ ---- + +clean_d_cache: + @ r0: cache clean area + bl receive_from_debugger + + mov r1, #1024 +clean_loop: + mcr p15, 0, r0, c7, c2, 5 + add r0, r0, #32 + subs r1, r1, #1 + bne clean_loop + + @ return + b get_command + +@ ---- + +invalidate_d_cache: + mcr p15, 0, r0, c7, c6, 0 + + @ return + b get_command + +@ ---- + +invalidate_i_cache: + mcr p15, 0, r0, c7, c5, 0 + + @ return + b get_command + +@ ---- + +cpwait: + m_cpwait + + @return + b get_command + +@ ---- + +.section .part2 , "ax" + +read_cp_reg: + @ requested cp register + bl receive_from_debugger + + adr r1, read_cp_table + add pc, r1, r0, lsl #3 + +read_cp_table: + mrc p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID + b read_cp_reg_reply + mrc p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE + b read_cp_reg_reply + mrc p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL + b read_cp_reg_reply + mrc p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL + b read_cp_reg_reply + mrc p15, 0, r0, c2, c0, 0 @ XSCALE_TTB + b read_cp_reg_reply + mrc p15, 0, r0, c3, c0, 0 @ XSCALE_DAC + b read_cp_reg_reply + mrc p15, 0, r0, c5, c0, 0 @ XSCALE_FSR + b read_cp_reg_reply + mrc p15, 0, r0, c6, c0, 0 @ XSCALE_FAR + b read_cp_reg_reply + mrc p15, 0, r0, c13, c0, 0 @ XSCALE_PID + b read_cp_reg_reply + mrc p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS + b read_cp_reg_reply + mrc p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 + b read_cp_reg_reply + mrc p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 + b read_cp_reg_reply + mrc p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 + b read_cp_reg_reply + mrc p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 + b read_cp_reg_reply + mrc p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON + b read_cp_reg_reply + mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG + b read_cp_reg_reply + mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 + b read_cp_reg_reply + mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 + b read_cp_reg_reply + mrc p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR + b read_cp_reg_reply + +read_cp_reg_reply: + bl send_to_debugger + + @ return + b get_command + +@ ---- + +write_cp_reg: + @ requested cp register + bl receive_from_debugger + mov r1, r0 + + @ value to be written + bl receive_from_debugger + + adr r2, write_cp_table + add pc, r2, r1, lsl #3 + +write_cp_table: + mcr p15, 0, r0, c0, c0, 0 @ XSCALE_MAINID (0x0) + b get_command + mcr p15, 0, r0, c0, c0, 1 @ XSCALE_CACHETYPE (0x1) + b get_command + mcr p15, 0, r0, c1, c0, 0 @ XSCALE_CTRL (0x2) + b get_command + mcr p15, 0, r0, c1, c0, 1 @ XSCALE_AUXCTRL (0x3) + b get_command + mcr p15, 0, r0, c2, c0, 0 @ XSCALE_TTB (0x4) + b get_command + mcr p15, 0, r0, c3, c0, 0 @ XSCALE_DAC (0x5) + b get_command + mcr p15, 0, r0, c5, c0, 0 @ XSCALE_FSR (0x6) + b get_command + mcr p15, 0, r0, c6, c0, 0 @ XSCALE_FAR (0x7) + b get_command + mcr p15, 0, r0, c13, c0, 0 @ XSCALE_PID (0x8) + b get_command + mcr p15, 0, r0, c15, c0, 0 @ XSCALE_CP_ACCESS (0x9) + b get_command + mcr p15, 0, r0, c14, c8, 0 @ XSCALE_IBCR0 (0xa) + b get_command + mcr p15, 0, r0, c14, c9, 0 @ XSCALE_IBCR1 (0xb) + b get_command + mcr p15, 0, r0, c14, c0, 0 @ XSCALE_DBR0 (0xc) + b get_command + mcr p15, 0, r0, c14, c3, 0 @ XSCALE_DBR1 (0xd) + b get_command + mcr p15, 0, r0, c14, c4, 0 @ XSCALE_DBCON (0xe) + b get_command + mcr p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG (0xf) + b get_command + mcr p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10) + b get_command + mcr p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11) + b get_command + mcr p14, 0, r0, c10, c0, 0 @ XSCALE_DCSR (0x12) + b get_command + +@ ---- + +read_trace_buffer: + + @ dump 256 entries from trace buffer + mov r1, #256 +read_tb_loop: + mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG + bl send_to_debugger + subs r1, r1, #1 + bne read_tb_loop + + @ dump checkpoint register 0 + mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10) + bl send_to_debugger + + @ dump checkpoint register 1 + mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11) + bl send_to_debugger + + @ return + b get_command + +@ ---- + +clean_trace_buffer: + + @ clean 256 entries from trace buffer + mov r1, #256 +clean_tb_loop: + mrc p14, 0, r0, c11, c0, 0 @ XSCALE_TBREG + subs r1, r1, #1 + bne clean_tb_loop + + @ return + b get_command + +@ ---- + + +@ resume program execution with trace buffer enabled +resume_w_trace: + @ restore CPSR (SPSR_dbg) + bl receive_from_debugger + msr spsr, r0 + + @ restore registers (r7 - r0) + bl receive_from_debugger @ r7 + mov r7, r0 + bl receive_from_debugger @ r6 + mov r6, r0 + bl receive_from_debugger @ r5 + mov r5, r0 + bl receive_from_debugger @ r4 + mov r4, r0 + bl receive_from_debugger @ r3 + mov r3, r0 + bl receive_from_debugger @ r2 + mov r2, r0 + bl receive_from_debugger @ r1 + mov r1, r0 + bl receive_from_debugger @ r0 + + @ resume addresss + m_receive_from_debugger lr + + mrc p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR + orr r13, r13, #1 + mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR + + @ branch back to application code, restoring CPSR + subs pc, lr, #0 + +undef_handler: +swi_handler: +prefetch_abort_handler: +data_abort_handler: +irq_handler: +fiq_handler: +1: + b 1b + +send_to_debugger: + m_send_to_debugger r0 + mov pc, lr + +receive_from_debugger: + m_receive_from_debugger r0 + mov pc, lr + diff --git a/contrib/loaders/debug/xscale/debug_handler.inc b/contrib/loaders/debug/xscale/debug_handler.inc new file mode 100644 index 0000000..d7f54e7 --- /dev/null +++ b/contrib/loaders/debug/xscale/debug_handler.inc @@ -0,0 +1,101 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x10,0xde,0x1a,0xee,0x02,0xd1,0x1d,0xe2,0x01,0x00,0x00,0x1a,0x03,0xd1,0xa0,0xe3, +0x10,0xde,0x0a,0xee,0x10,0xfe,0x1e,0xee,0xfd,0xff,0xff,0x6a,0x10,0x0e,0x08,0xee, +0x10,0xfe,0x1e,0xee,0xfd,0xff,0xff,0x6a,0x10,0xee,0x08,0xee,0x01,0x00,0xa0,0xe1, +0x70,0x01,0x00,0xeb,0x02,0x00,0xa0,0xe1,0x6e,0x01,0x00,0xeb,0x03,0x00,0xa0,0xe1, +0x6c,0x01,0x00,0xeb,0x04,0x00,0xa0,0xe1,0x6a,0x01,0x00,0xeb,0x05,0x00,0xa0,0xe1, +0x68,0x01,0x00,0xeb,0x06,0x00,0xa0,0xe1,0x66,0x01,0x00,0xeb,0x07,0x00,0xa0,0xe1, +0x64,0x01,0x00,0xeb,0x00,0x00,0x4f,0xe1,0x62,0x01,0x00,0xeb,0x00,0x00,0x4f,0xe1, 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+0x00,0x50,0xa0,0xe1,0x13,0x00,0x00,0xeb,0x00,0x40,0xa0,0xe1,0x11,0x00,0x00,0xeb, +0x00,0x30,0xa0,0xe1,0x0f,0x00,0x00,0xeb,0x00,0x20,0xa0,0xe1,0x0d,0x00,0x00,0xeb, +0x00,0x10,0xa0,0xe1,0x0b,0x00,0x00,0xeb,0x10,0xfe,0x1e,0xee,0xfd,0xff,0xff,0x5a, +0x10,0xee,0x19,0xee,0x10,0xde,0x1a,0xee,0x01,0xd0,0x8d,0xe3,0x10,0xde,0x0a,0xee, +0x00,0xf0,0x5e,0xe2,0xfe,0xff,0xff,0xea,0x10,0xfe,0x1e,0xee,0xfd,0xff,0xff,0x6a, +0x10,0x0e,0x08,0xee,0x0e,0xf0,0xa0,0xe1,0x10,0xfe,0x1e,0xee,0xfd,0xff,0xff,0x5a, +0x10,0x0e,0x19,0xee,0x0e,0xf0,0xa0,0xe1, diff --git a/contrib/loaders/debug/xscale/debug_handler.ld b/contrib/loaders/debug/xscale/debug_handler.ld new file mode 100644 index 0000000..d943b13 --- /dev/null +++ b/contrib/loaders/debug/xscale/debug_handler.ld @@ -0,0 +1,49 @@ +/* identify the Entry Point */ +ENTRY(reset_handler) + +/* specify the mini-ICache memory areas */ +MEMORY +{ + mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */ + mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */ +} + +/* now define the output sections */ +SECTIONS +{ + .part1 : + { + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + *(.part1) + } >mini_icache_0 + + .part2 : + { + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + LONG(0) + *(.part2) + FILL(0x0) + } >mini_icache_1 + + /DISCARD/ : + { + *(.text) + *(.glue_7) + *(.glue_7t) + *(.data) + *(.bss) + } +} diff --git a/contrib/loaders/debug/xscale/protocol.h b/contrib/loaders/debug/xscale/protocol.h new file mode 100644 index 0000000..cb01655 --- /dev/null +++ b/contrib/loaders/debug/xscale/protocol.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2006 by Dominic Rath * + * Dominic.Rath@gmx.de * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program. If not, see <http://www.gnu.org/licenses/>. * + ***************************************************************************/ + +#define REG_R0 0 +#define REG_R1 1 +#define REG_R2 2 +#define REG_R3 3 +#define REG_R4 4 +#define REG_R5 5 +#define REG_R6 6 +#define REG_R7 7 +#define REG_R8 8 +#define REG_R9 9 +#define REG_R10 10 +#define REG_R11 11 +#define REG_R12 12 +#define REG_R13 13 +#define REG_R14 14 +#define REG_R15 15 +#define REG_CPSR 16 +#define REG_SPSR 17 + +#define MODE_USR 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_ABT 0x17 +#define MODE_UND 0x1b +#define MODE_SYS 0x1f + +#define MODE_ANY 0x40 +#define MODE_CURRENT 0x80 + +#define MODE_MASK 0x1f +#define PSR_I 0x80 +#define PSR_F 0x40 +#define PSR_T 0x20 + +#define XSCALE_DBG_MAINID 0x0 +#define XSCALE_DBG_CACHETYPE 0x1 +#define XSCALE_DBG_CTRL 0x2 +#define XSCALE_DBG_AUXCTRL 0x3 +#define XSCALE_DBG_TTB 0x4 +#define XSCALE_DBG_DAC 0x5 +#define XSCALE_DBG_FSR 0x6 +#define XSCALE_DBG_FAR 0x7 +#define XSCALE_DBG_PID 0x8 +#define XSCALE_DBG_CPACCESS 0x9 +#define XSCALE_DBG_IBCR0 0xa +#define XSCALE_DBG_IBCR1 0xb +#define XSCALE_DBG_DBR0 0xc +#define XSCALE_DBG_DBR1 0xd +#define XSCALE_DBG_DBCON 0xe diff --git a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py index a107a6a..fa4ec2a 100755 --- a/contrib/loaders/flash/fpga/xilinx_bscan_spi.py +++ b/contrib/loaders/flash/fpga/xilinx_bscan_spi.py @@ -13,20 +13,21 @@ # GNU General Public License for more details. # -from migen.fhdl.std import * -from mibuild.generic_platform import * -from mibuild.xilinx import XilinxPlatform -from mibuild.xilinx.vivado import XilinxVivadoToolchain -from mibuild.xilinx.ise import XilinxISEToolchain +from migen import * +from migen.build.generic_platform import * +from migen.build import xilinx """ This migen script produces proxy bitstreams to allow programming SPI flashes -behind FPGAs. JTAG signalling is connected directly to SPI signalling. CS_N is -asserted when the JTAG IR contains the USER1 instruction and the state is -SHIFT-DR. +behind FPGAs. + +Bitstream binaries built with this script are available at: +https://github.com/jordens/bscan_spi_bitstreams -Xilinx bscan cells sample TDO on falling TCK and forward it. +JTAG signalling is connected directly to SPI signalling. CS_N is +asserted when the JTAG IR contains the USER1 instruction and the state is +SHIFT-DR. Xilinx bscan cells sample TDO on falling TCK and forward it. MISO requires sampling on rising CLK and leads to one cycle of latency. https://github.com/m-labs/migen @@ -35,8 +36,10 @@ https://github.com/m-labs/migen class Spartan3(Module): macro = "BSCAN_SPARTAN3" + toolchain = "ise" def __init__(self, platform): + platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup" self.clock_domains.cd_jtag = ClockDomain(reset_less=True) spi = platform.request("spiflash") shift = Signal() @@ -58,7 +61,10 @@ class Spartan3A(Spartan3): class Spartan6(Module): + toolchain = "ise" + def __init__(self, platform): + platform.toolchain.bitgen_opt += " -g compress -g UnusedPin:Pullup" self.clock_domains.cd_jtag = ClockDomain(reset_less=True) spi = platform.request("spiflash") shift = Signal() @@ -72,7 +78,13 @@ class Spartan6(Module): class Series7(Module): + toolchain = "vivado" + def __init__(self, platform): + platform.toolchain.bitstream_commands.extend([ + "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", + "set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]", + ]) self.clock_domains.cd_jtag = ClockDomain(reset_less=True) spi = platform.request("spiflash") clk = Signal() @@ -89,184 +101,105 @@ class Series7(Module): i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1) -class XilinxBscanSpi(XilinxPlatform): +class XilinxBscanSpi(xilinx.XilinxPlatform): + packages = { + # (package-speedgrade, id): [cs_n, clk, mosi, miso, *pullups] + ("cp132", 1): ["M2", "N12", "N2", "N8"], + ("fg320", 1): ["U3", "U16", "T4", "N10"], + ("fg320", 2): ["V3", "U16", "T11", "V16"], + ("fg484", 1): ["Y4", "AA20", "AB14", "AB20"], + ("fgg484", 1): ["Y4", "AA20", "AB14", "AB20"], + ("fgg400", 1): ["Y2", "Y19", "W12", "W18"], + ("ftg256", 1): ["T2", "R14", "P10", "T14"], + ("ft256", 1): ["T2", "R14", "P10", "T14"], + ("fg400", 1): ["Y2", "Y19", "W12", "W18"], + ("cs484", 1): ["U7", "V17", "V13", "W17"], + ("qg144-2", 1): ["P38", "P70", "P64", "P65", "P62", "P61"], + ("cpg196-2", 1): ["P2", "N13", "P11", "N11", "N10", "P10"], + ("cpg236-1", 1): ["K19", None, "D18", "D19", "G18", "F18"], + ("csg484-2", 1): ["AB5", "W17", "AB17", "Y17", "V13", "W13"], + ("csg324-2", 1): ["V3", "R15", "T13", "R13", "T14", "V14"], + ("csg324-1", 1): ["L13", None, "K17", "K18", "L14", "M14"], + ("fbg484-1", 1): ["T19", None, "P22", "R22", "P21", "R21"], + ("fbg484-1", 2): ["L16", None, "H18", "H19", "G18", "F19"], + ("fbg676-1", 1): ["C23", None, "B24", "A25", "B22", "A22"], + ("ffg901-1", 1): ["V26", None, "R30", "T30", "R28", "T28"], + ("ffg1156-1", 1): ["V30", None, "AA33", "AA34", "Y33", "Y34"], + ("ffg1157-1", 1): ["AL33", None, "AN33", "AN34", "AK34", "AL34"], + ("ffg1158-1", 1): ["C24", None, "A23", "A24", "B26", "A26"], + ("ffg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"], + ("fhg1761-1", 1): ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"], + ("flg1155-1", 1): ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"], + ("flg1932-1", 1): ["V32", None, "T33", "R33", "U31", "T31"], + ("flg1926-1", 1): ["AK33", None, "AN34", "AN35", "AJ34", "AK34"], + } + pinouts = { # bitstreams are named by die, package does not matter, speed grade # should not matter. - # cs_n, clk, mosi, miso, *pullups - "xc3s100e": ("cp132", - ["M2", "N12", "N2", "N8"], - "LVCMOS33", Spartan3), - "xc3s1200e": ("fg320", - ["U3", "U16", "T4", "N10"], - "LVCMOS33", Spartan3), - "xc3s1400a": ("fg484", - ["Y4", "AA20", "AB14", "AB20"], - "LVCMOS33", Spartan3A), - "xc3s1400an": ("fgg484", - ["Y4", "AA20", "AB14", "AB20"], - "LVCMOS33", Spartan3A), - "xc3s1600e": ("fg320", - ["U3", "U16", "T4", "N10"], - "LVCMOS33", Spartan3), - "xc3s200a": ("fg320", - ["V3", "U16", "T11", "V16"], - "LVCMOS33", Spartan3A), - "xc3s200an": ("ftg256", - ["T2", "R14", "P10", "T14"], - "LVCMOS33", Spartan3A), - "xc3s250e": ("cp132", - ["M2", "N12", "N2", "N8"], - "LVCMOS33", Spartan3), - "xc3s400a": ("fg320", - ["V3", "U16", "T11", "V16"], - "LVCMOS33", Spartan3A), - "xc3s400an": ("fgg400", - ["Y2", "Y19", "W12", "W18"], - "LVCMOS33", Spartan3A), - "xc3s500e": ("cp132", - ["M2", "N12", "N2", "N8"], - "LVCMOS33", Spartan3), - "xc3s50a": ("ft256", - ["T2", "R14", "P10", "T14"], - "LVCMOS33", Spartan3A), - "xc3s50an": ("ftg256", - ["T2", "R14", "P10", "T14"], - "LVCMOS33", Spartan3A), - "xc3s700a": ("fg400", - ["Y2", "Y19", "W12", "W18"], - "LVCMOS33", Spartan3A), - "xc3s700an": ("fgg484", - ["Y4", "AA20", "AB14", "AB20"], - "LVCMOS33", Spartan3A), - "xc3sd1800a": ("cs484", - ["U7", "V17", "V13", "W17"], - "LVCMOS33", Spartan3A), - "xc3sd3400a": ("cs484", - ["U7", "V17", "V13", "W17"], - "LVCMOS33", Spartan3A), - - "xc6slx100": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx100t": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx150": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx150t": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx16": ("cpg196-2", - ["P2", "N13", "P11", "N11", "N10", "P10"], - "LVCMOS33", Spartan6), - "xc6slx25": ("csg324-2", - ["V3", "R15", "T13", "R13", "T14", "V14"], - "LVCMOS33", Spartan6), - "xc6slx25t": ("csg324-2", - ["V3", "R15", "T13", "R13", "T14", "V14"], - "LVCMOS33", Spartan6), - "xc6slx45": ("csg324-2", - ["V3", "R15", "T13", "R13", "T14", "V14"], - "LVCMOS33", Spartan6), - "xc6slx45t": ("csg324-2", - ["V3", "R15", "T13", "R13", "T14", "V14"], - "LVCMOS33", Spartan6), - "xc6slx4": ("cpg196-2", - ["P2", "N13", "P11", "N11", "N10", "P10"], - "LVCMOS33", Spartan6), - "xc6slx4t": ("qg144-2", - ["P38", "P70", "P64", "P65", "P62", "P61"], - "LVCMOS33", Spartan6), - "xc6slx75": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx75t": ("csg484-2", - ["AB5", "W17", "AB17", "Y17", "V13", "W13"], - "LVCMOS33", Spartan6), - "xc6slx9": ("cpg196-2", - ["P2", "N13", "P11", "N11", "N10", "P10"], - "LVCMOS33", Spartan6), - "xc6slx9t": ("qg144-2", - ["P38", "P70", "P64", "P65", "P62", "P61"], - "LVCMOS33", Spartan6), - - "xc7a100t": ("csg324-1", - ["L13", None, "K17", "K18", "L14", "M14"], - "LVCMOS25", Series7), - "xc7a15t": ("cpg236-1", - ["K19", None, "D18", "D19", "G18", "F18"], - "LVCMOS25", Series7), - "xc7a200t": ("fbg484-1", - ["T19", None, "P22", "R22", "P21", "R21"], - "LVCMOS25", Series7), - "xc7a35t": ("cpg236-1", - ["K19", None, "D18", "D19", "G18", "F18"], - "LVCMOS25", Series7), - "xc7a50t": ("cpg236-1", - ["K19", None, "D18", "D19", "G18", "F18"], - "LVCMOS25", Series7), - "xc7a75t": ("csg324-1", - ["L13", None, "K17", "K18", "L14", "M14"], - "LVCMOS25", Series7), - "xc7k160t": ("fbg484-1", - ["L16", None, "H18", "H19", "G18", "F19"], - "LVCMOS25", Series7), - "xc7k325t": ("fbg676-1", - ["C23", None, "B24", "A25", "B22", "A22"], - "LVCMOS25", Series7), - "xc7k355t": ("ffg901-1", - ["V26", None, "R30", "T30", "R28", "T28"], - "LVCMOS25", Series7), - "xc7k410t": ("fbg676-1", - ["C23", None, "B24", "A25", "B22", "A22"], - "LVCMOS25", Series7), - "xc7k420t": ("ffg1156-1", - ["V30", None, "AA33", "AA34", "Y33", "Y34"], - "LVCMOS25", Series7), - "xc7k480t": ("ffg1156-1", - ["V30", None, "AA33", "AA34", "Y33", "Y34"], - "LVCMOS25", Series7), - "xc7k70t": ("fbg484-1", - ["L16", None, "H18", "H19", "G18", "F19"], - "LVCMOS25", Series7), - "xc7v2000t": ("fhg1761-1", - ["AL36", None, "AM36", "AN36", "AJ36", "AJ37"], - "LVCMOS18", Series7), - "xc7v585t": ("ffg1157-1", - ["AL33", None, "AN33", "AN34", "AK34", "AL34"], - "LVCMOS18", Series7), - "xc7vh580t": ("flg1155-1", - ["AL28", None, "AE28", "AF28", "AJ29", "AJ30"], - "LVCMOS18", Series7), - "xc7vh870t": ("flg1932-1", - ["V32", None, "T33", "R33", "U31", "T31"], - "LVCMOS18", Series7), - "xc7vx1140t": ("flg1926-1", - ["AK33", None, "AN34", "AN35", "AJ34", "AK34"], - "LVCMOS18", Series7), - "xc7vx330t": ("ffg1157-1", - ["AL33", None, "AN33", "AN34", "AK34", "AL34"], - "LVCMOS18", Series7), - "xc7vx415t": ("ffg1157-1", - ["AL33", None, "AN33", "AN34", "AK34", "AL34"], - "LVCMOS18", Series7), - "xc7vx485t": ("ffg1157-1", - ["AL33", None, "AN33", "AN34", "AK34", "AL34"], - "LVCMOS18", Series7), - "xc7vx550t": ("ffg1158-1", - ["C24", None, "A23", "A24", "B26", "A26"], - "LVCMOS18", Series7), - "xc7vx690t": ("ffg1157-1", - ["AL33", None, "AN33", "AN34", "AK34", "AL34"], - "LVCMOS18", Series7), - "xc7vx980t": ("ffg1926-1", - ["AK33", None, "AN34", "AN35", "AJ34", "AK34"], - "LVCMOS18", Series7), + # + # chip: (package, id, standard, class) + "xc3s100e": ("cp132", 1, "LVCMOS33", Spartan3), + "xc3s1200e": ("fg320", 1, "LVCMOS33", Spartan3), + "xc3s1400a": ("fg484", 1, "LVCMOS33", Spartan3A), + "xc3s1400an": ("fgg484", 1, "LVCMOS33", Spartan3A), + "xc3s1600e": ("fg320", 1, "LVCMOS33", Spartan3), + "xc3s200a": ("fg320", 2, "LVCMOS33", Spartan3A), + "xc3s200an": ("ftg256", 1, "LVCMOS33", Spartan3A), + "xc3s250e": ("cp132", 1, "LVCMOS33", Spartan3), + "xc3s400a": ("fg320", 2, "LVCMOS33", Spartan3A), + "xc3s400an": ("fgg400", 1, "LVCMOS33", Spartan3A), + "xc3s500e": ("cp132", 1, "LVCMOS33", Spartan3), + "xc3s50a": ("ft256", 1, "LVCMOS33", Spartan3A), + "xc3s50an": ("ftg256", 1, "LVCMOS33", Spartan3A), + "xc3s700a": ("fg400", 1, "LVCMOS33", Spartan3A), + "xc3s700an": ("fgg484", 1, "LVCMOS33", Spartan3A), + "xc3sd1800a": ("cs484", 1, "LVCMOS33", Spartan3A), + "xc3sd3400a": ("cs484", 1, "LVCMOS33", Spartan3A), + + "xc6slx100": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx100t": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx150": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx150t": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx16": ("cpg196-2", 1, "LVCMOS33", Spartan6), + "xc6slx25": ("csg324-2", 1, "LVCMOS33", Spartan6), + "xc6slx25t": ("csg324-2", 1, "LVCMOS33", Spartan6), + "xc6slx45": ("csg324-2", 1, "LVCMOS33", Spartan6), + "xc6slx45t": ("csg324-2", 1, "LVCMOS33", Spartan6), + "xc6slx4": ("cpg196-2", 1, "LVCMOS33", Spartan6), + "xc6slx4t": ("qg144-2", 1, "LVCMOS33", Spartan6), + "xc6slx75": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx75t": ("csg484-2", 1, "LVCMOS33", Spartan6), + "xc6slx9": ("cpg196-2", 1, "LVCMOS33", Spartan6), + "xc6slx9t": ("qg144-2", 1, "LVCMOS33", Spartan6), + + "xc7a100t": ("csg324-1", 1, "LVCMOS25", Series7), + "xc7a15t": ("cpg236-1", 1, "LVCMOS25", Series7), + "xc7a200t": ("fbg484-1", 1, "LVCMOS25", Series7), + "xc7a35t": ("cpg236-1", 1, "LVCMOS25", Series7), + "xc7a50t": ("cpg236-1", 1, "LVCMOS25", Series7), + "xc7a75t": ("csg324-1", 1, "LVCMOS25", Series7), + "xc7k160t": ("fbg484-1", 2, "LVCMOS25", Series7), + "xc7k325t": ("fbg676-1", 1, "LVCMOS25", Series7), + "xc7k355t": ("ffg901-1", 1, "LVCMOS25", Series7), + "xc7k410t": ("fbg676-1", 1, "LVCMOS25", Series7), + "xc7k420t": ("ffg1156-1", 1, "LVCMOS25", Series7), + "xc7k480t": ("ffg1156-1", 1, "LVCMOS25", Series7), + "xc7k70t": ("fbg484-1", 2, "LVCMOS25", Series7), + "xc7v2000t": ("fhg1761-1", 1, "LVCMOS18", Series7), + "xc7v585t": ("ffg1157-1", 1, "LVCMOS18", Series7), + "xc7vh580t": ("flg1155-1", 1, "LVCMOS18", Series7), + "xc7vh870t": ("flg1932-1", 1, "LVCMOS18", Series7), + "xc7vx1140t": ("flg1926-1", 1, "LVCMOS18", Series7), + "xc7vx330t": ("ffg1157-1", 1, "LVCMOS18", Series7), + "xc7vx415t": ("ffg1157-1", 1, "LVCMOS18", Series7), + "xc7vx485t": ("ffg1157-1", 1, "LVCMOS18", Series7), + "xc7vx550t": ("ffg1158-1", 1, "LVCMOS18", Series7), + "xc7vx690t": ("ffg1157-1", 1, "LVCMOS18", Series7), + "xc7vx980t": ("ffg1926-1", 1, "LVCMOS18", Series7), } - def __init__(self, device, pins, std): + def __init__(self, device, pins, std, toolchain="ise"): cs_n, clk, mosi, miso = pins[:4] io = ["spiflash", 0, Subsignal("cs_n", Pins(cs_n)), @@ -278,26 +211,21 @@ class XilinxBscanSpi(XilinxPlatform): io.append(Subsignal("clk", Pins(clk))) for i, p in enumerate(pins[4:]): io.append(Subsignal("pullup{}".format(i), Pins(p), Misc("PULLUP"))) - - XilinxPlatform.__init__(self, device, [io]) - if isinstance(self.toolchain, XilinxVivadoToolchain): - self.toolchain.bitstream_commands.append( - "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]" - ) - elif isinstance(self.toolchain, XilinxISEToolchain): - self.toolchain.bitgen_opt += " -g compress" + xilinx.XilinxPlatform.__init__(self, device, [io], toolchain=toolchain) @classmethod def make(cls, device, errors=False): - pkg, pins, std, Top = cls.pinouts[device] - platform = cls("{}-{}".format(device, pkg), pins, std) + pkg, id, std, Top = cls.pinouts[device] + pins = cls.packages[(pkg, id)] + platform = cls("{}-{}".format(device, pkg), pins, std, Top.toolchain) top = Top(platform) name = "bscan_spi_{}".format(device) dir = "build_{}".format(device) try: platform.build(top, build_name=name, build_dir=dir) except Exception as e: - print("ERROR: build failed for {}: {}".format(device, e)) + print(("ERROR: xilinx_bscan_spi build failed " + "for {}: {}").format(device, e)) if errors: raise diff --git a/contrib/loaders/flash/kinetis/Makefile b/contrib/loaders/flash/kinetis/Makefile new file mode 100644 index 0000000..b240f53 --- /dev/null +++ b/contrib/loaders/flash/kinetis/Makefile @@ -0,0 +1,19 @@ +BIN2C = ../../../../src/helper/bin2char.sh + +CROSS_COMPILE ?= arm-none-eabi- +AS = $(CROSS_COMPILE)as +OBJCOPY = $(CROSS_COMPILE)objcopy + +all: kinetis_flash.inc + +%.elf: %.s + $(AS) $< -o $@ + +%.bin: %.elf + $(OBJCOPY) -Obinary $< $@ + +%.inc: %.bin + $(BIN2C) < $< > $@ + +clean: + -rm -f *.elf *.bin *.inc diff --git a/contrib/loaders/flash/kinetis/kinetis_flash.inc b/contrib/loaders/flash/kinetis/kinetis_flash.inc new file mode 100644 index 0000000..c93797b --- /dev/null +++ b/contrib/loaders/flash/kinetis/kinetis_flash.inc @@ -0,0 +1,6 @@ +/* Autogenerated with ../../../../src/helper/bin2char.sh */ +0x16,0x68,0x00,0x2e,0x1f,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,0x60,0x60,0x06,0x27, +0xe7,0x71,0x2f,0x68,0xa7,0x60,0x80,0x27,0x27,0x70,0x04,0x35,0x9d,0x42,0x01,0xd3, +0x15,0x1c,0x08,0x35,0x55,0x60,0x16,0x68,0x00,0x2e,0x0c,0xd0,0x26,0x78,0x3e,0x42, +0xf9,0xd0,0x70,0x27,0x3e,0x42,0x04,0xd1,0x04,0x30,0x01,0x39,0x00,0x29,0xdf,0xd1, +0x01,0xe0,0x00,0x25,0x55,0x60,0x00,0xbe, diff --git a/contrib/loaders/flash/kinetis/kinetis_flash.s b/contrib/loaders/flash/kinetis/kinetis_flash.s new file mode 100644 index 0000000..c8e6e05 --- /dev/null +++ b/contrib/loaders/flash/kinetis/kinetis_flash.s @@ -0,0 +1,101 @@ +/*************************************************************************** + * Copyright (C) 2015 by Ivan Meleca * + * ivan@artekit.eu * + * * + * Copyright (C) 2016 by Tomas Vanek * + * vanekt@fbl.cz * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + ***************************************************************************/ + + /* Params: + * r0 = flash destination address in/out + * r1 = longword count + * r2 = workarea start address + * r3 = workarea end address + * r4 = FTFx base + */ + + .text + .cpu cortex-m0plus + .code 16 + .thumb_func + + .align 2 + + /* r5 = rp + * r6 = wp, tmp + * r7 = tmp + */ + + /* old longword algo: 6.680 KiB/s @ adapter_khz 2000 + * this async algo: 19.808 KiB/s @ adapter_khz 2000 + */ + +FTFx_FSTAT = 0 +FTFx_FCCOB3 = 4 +FTFx_FCCOB0 = 7 +FTFx_FCCOB7 = 8 + +wait_fifo: + ldr r6, [r2, #0] /* read wp */ + cmp r6, #0 /* abort if wp == 0 */ + beq exit + + ldr r5, [r2, #4] /* read rp */ + cmp r5, r6 /* wait until rp != wp */ + beq wait_fifo + + str r0, [r4, #FTFx_FCCOB3] /* set flash address */ + mov r7, #6 + strb r7, [r4, #FTFx_FCCOB0] /* flash command */ + + ldr r7, [r5] /* set longword data = *rp */ + str r7, [r4, #FTFx_FCCOB7] + + mov r7, #128 + strb r7, [r4, #FTFx_FSTAT] + + add r5, #4 /* rp += 4 */ + cmp r5, r3 /* Wrap? */ + bcc no_wrap + mov r5, r2 + add r5, #8 + +no_wrap: + str r5, [r2, #4] /* Store rp */ + +wait_ccif: + ldr r6, [r2, #0] /* read wp */ + cmp r6, #0 /* abort if wp == 0 */ + beq exit + + ldrb r6, [r4, #FTFx_FSTAT] + tst r6, r7 + beq wait_ccif + + mov r7, #0x70 + tst r6, r7 + bne error + + add r0, #4 /* flash address += 4, do not increment before err check */ + + sub r1, #1 /* word_count-- */ + cmp r1, #0 + bne wait_fifo + b exit + +error: + mov r5, #0 + str r5, [r2, #4] /* set rp = 0 on error */ + +exit: + bkpt #0 diff --git a/contrib/loaders/flash/stm32lx.S b/contrib/loaders/flash/stm32lx.S index 88deed3..8f9fd0b 100644 --- a/contrib/loaders/flash/stm32lx.S +++ b/contrib/loaders/flash/stm32lx.S @@ -8,6 +8,9 @@ * Copyright (C) 2011 Clement Burin des Roziers * * clement.burin-des-roziers@hikob.com * * * + * Copyright (C) 2017 Armin van der Togt * + * armin@otheruse.nl * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -28,7 +31,7 @@ // Build : arm-eabi-gcc -c stm32lx.S .text .syntax unified - .cpu cortex-m3 + .cpu cortex-m0 .thumb .thumb_func .global write @@ -39,24 +42,21 @@ r2 - count */ - // Set 0 to r3 - movs r3, #0 + // r2 = source + count * 4 + lsls r2, r2, #2 + adds r2, r1, r2 // Go to compare - b.n test_done - + b test_done write_word: - // Load one word from address in r0, increment by 4 - ldr.w ip, [r1], #4 - // Store the word to address in r1, increment by 4 - str.w ip, [r0], #4 - // Increment r3 - adds r3, #1 - + // load word from address in r1 and increase r1 by 4 + ldmia r1!, {r3} + // store word to address in r0 and increase r0 by 4 + stmia r0!, {r3} test_done: - // Compare r3 and r2 - cmp r3, r2 - // Loop if not zero - bcc.n write_word + // compare r1 and r2 + cmp r1, r2 + // loop if not equal + bne write_word // Set breakpoint to exit bkpt #0x00 |