pld: add support for altera/intel devices

Change-Id: I7977d39c9037ae71139f78c8d381f5f925dc3489
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7355
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

13 files changed, 304 insertions, 49 deletions

diff --git a/tcl/board/bemicro_cycloneiii.cfg b/tcl/board/bemicro_cycloneiii.cfg
new file mode 100644
index 0000000..7781bd5
--- /dev/null
+++ b/tcl/board/bemicro_cycloneiii.cfg
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# BeMicro Cyclone III
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0xa4a0
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find cpld/altera-cycloneiii.cfg]
+
+#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
+
+#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load 0 cycloneiii_blinker.rbf"
+# "ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555"
diff --git a/tcl/cpld/altera-5m570z-cpld.cfg b/tcl/cpld/altera-5m570z-cpld.cfg
index 5dbd0de..4504a80 100644
--- a/tcl/cpld/altera-5m570z-cpld.cfg
+++ b/tcl/cpld/altera-5m570z-cpld.cfg
@@ -1,8 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# Altera MAXV 5M24OZ/5M570Z CPLD
-# see MAX V Device Handbook
-# Table 6-3: 32-Bit MAX V Device IDCODE
-# Version     Part Number             Manuf. ID        LSB
-# 0000        0010 0000 1010 0111     000 0110 1110    1
-jtag newtap 5m570z tap -expected-id 0x020a60dd -irlen 10
+# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg
+echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg"
+
+#just to be backward compatible:
+#tap will be 5m570z.tap instead of maxv.tap:
+set CHIPNAME 5m570z
+source [find cpld/altera-maxv.cfg]
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index 39c409b..185925a 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -1,24 +1,12 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# Altera MAXII EPM240T100C CPLD
+# file altera-epm240.cfg replaced by altera-maxii.cfg
+echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg"
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME epm240
-}
-
-# see MAX II Device Handbook
-# Table 3-3: 32-Bit MAX II Device IDCODE
-# Version     Part Number             Manuf. ID        LSB
-# 0000        0010 0000 1010 0001     000 0110 1110    1
-jtag newtap $_CHIPNAME tap -irlen 10 \
-	-expected-id 0x020a10dd \
-	-expected-id 0x020a20dd \
-	-expected-id 0x020a30dd \
-	-expected-id 0x020a40dd \
-	-expected-id 0x020a50dd \
-	-expected-id 0x020a60dd
+#just to be backward compatible:
+#tap will be epm240.tap instead of maxii.tap:
+set CHIPNAME epm240
+source [find cpld/altera-maxii.cfg]
 
 # 200ns seems like a good speed
 # c.f. Table 5-34: MAX II JTAG Timing Parameters
diff --git a/tcl/cpld/altera-max10.cfg b/tcl/cpld/altera-max10.cfg
new file mode 100644
index 0000000..a2ed00a
--- /dev/null
+++ b/tcl/cpld/altera-max10.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# see MAX 10 FPGA Device Architecture
+# Table 3-1: IDCODE Information for MAX 10 Devices
+# Intel MAX 10M02 0x31810dd
+# Intel MAX 10M04 0x318a0dd
+# Intel MAX 10M08 0x31820dd
+# Intel MAX 10M16 0x31830dd
+# Intel MAX 10M25 0x31840dd
+# Intel MAX 10M40 0x318d0dd
+# Intel MAX 10M50 0x31850dd
+# Intel MAX 10M02 0x31010dd
+# Intel MAX 10M04 0x310a0dd
+# Intel MAX 10M08 0x31020dd
+# Intel MAX 10M16 0x31030dd
+# Intel MAX 10M25 0x31040dd
+# Intel MAX 10M40 0x310d0dd
+# Intel MAX 10M50 0x31050dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME max10
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
+	-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
+	-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
+	-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
+	-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
diff --git a/tcl/cpld/altera-maxii.cfg b/tcl/cpld/altera-maxii.cfg
new file mode 100644
index 0000000..2dee37f
--- /dev/null
+++ b/tcl/cpld/altera-maxii.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXII CPLD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxii
+}
+
+# see MAX II Device Handbook
+# Table 3-3: 32-Bit MAX II Device IDCODE
+# Version     Part Number             Manuf. ID        LSB
+# 0000        0010 0000 1010 0001     000 0110 1110    1
+jtag newtap $_CHIPNAME tap -irlen 10 \
+	-expected-id 0x020a10dd \
+	-expected-id 0x020a20dd \
+	-expected-id 0x020a30dd \
+	-expected-id 0x020a40dd \
+	-expected-id 0x020a50dd \
+	-expected-id 0x020a60dd
diff --git a/tcl/cpld/altera-maxv.cfg b/tcl/cpld/altera-maxv.cfg
new file mode 100644
index 0000000..03fad07
--- /dev/null
+++ b/tcl/cpld/altera-maxv.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Altera MAXV 5M24OZ/5M570Z CPLD
+# see MAX V Device Handbook
+# Table 6-3: 32-Bit MAX V Device IDCODE
+# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD
+# 5M570Z:                    0x020A60DD
+# 5M1270Z:                   0x020A30DD
+# 5M1270Z 5M2210Z:           0x020A40DD
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME maxv
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x020A50DD -expected-id 0x020A60DD \
+  -expected-id 0x020A30DD -expected-id 0x020A40DD
diff --git a/tcl/fpga/altera-10m50.cfg b/tcl/fpga/altera-10m50.cfg
index 1937cb4..94228d2 100644
--- a/tcl/fpga/altera-10m50.cfg
+++ b/tcl/fpga/altera-10m50.cfg
@@ -1,24 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# see MAX 10 FPGA Device Architecture
-# Table 3-1: IDCODE Information for MAX 10 Devices
-# Intel MAX 10M02 0x31810dd
-# Intel MAX 10M04 0x318a0dd
-# Intel MAX 10M08 0x31820dd
-# Intel MAX 10M16 0x31830dd
-# Intel MAX 10M25 0x31840dd
-# Intel MAX 10M40 0x318d0dd
-# Intel MAX 10M50 0x31850dd
-# Intel MAX 10M02 0x31010dd
-# Intel MAX 10M04 0x310a0dd
-# Intel MAX 10M08 0x31020dd
-# Intel MAX 10M16 0x31030dd
-# Intel MAX 10M25 0x31040dd
-# Intel MAX 10M40 0x310d0dd
-# Intel MAX 10M50 0x31050dd
+# file altera-10m50.cfg replaced by altera-max10.cfg
+echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg"
 
-jtag newtap 10m50 tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
-	-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
-	-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
-	-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
-	-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
+#just to be backward compatible:
+#tap will be 10m50.tap instead of max10.tap:
+set CHIPNAME 10m50
+source [find cpld/altera-max10.cfg]
diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg
new file mode 100644
index 0000000..ae752df
--- /dev/null
+++ b/tcl/fpga/altera-arriaii.cfg
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Arria II FPGA
+# Arria II Device Handbook
+# Table 11–2. 32-Bit IDCODE for Arria II Devices
+
+#GX:
+#EP2AGX45:  0x025120dd
+#EP2AGX65:  0x025020dd
+#EP2AGX95:  0x025130dd
+#EP2AGX125: 0x025030dd
+#EP2AGX190: 0x025140dd
+#EP2AGX260: 0x025040dd
+#EP2AGZ225: 0x024810dd
+#EP2AGZ300: 0x0240a0dd
+#EP2AGZ350: 0x024820dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arriaii
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x025120dd -expected-id 0x025040dd \
+  -expected-id 0x025020dd -expected-id 0x024810dd \
+  -expected-id 0x025130dd -expected-id 0x0240a0dd \
+  -expected-id 0x025030dd -expected-id 0x024820dd \
+  -expected-id 0x025140dd
+
+pld device intel $_CHIPNAME.tap arriaii
diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg
new file mode 100644
index 0000000..3a1bc1f
--- /dev/null
+++ b/tcl/fpga/altera-cyclone10.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 10 FPGA
+# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
+# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
+
+# GX085: 0x02e120dd
+# GX105: 0x02e320dd
+# GX150: 0x02e720dd
+# GX220: 0x02ef20dd
+# 10cl006: 0x020f10dd
+# 10cl010: 0x020f10dd
+# 10cl016: 0x020f20dd
+# 10cl025: 0x020f30dd
+# 10cl040: 0x020f40dd
+# 10cl055: 0x020f50dd
+# 10cl080: 0x020f60dd
+# 10cl120: 0x020f70dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclone10
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x02e720dd -expected-id 0x02e120dd \
+  -expected-id 0x02ef20dd -expected-id 0x02e320dd \
+  -expected-id 0x020f10dd -expected-id 0x020f20dd \
+  -expected-id 0x020f30dd -expected-id 0x020f40dd \
+  -expected-id 0x020f50dd -expected-id 0x020f60dd \
+  -expected-id 0x020f70dd
+
+pld device intel $_CHIPNAME.tap cyclone10
diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg
new file mode 100644
index 0000000..e143572
--- /dev/null
+++ b/tcl/fpga/altera-cycloneiii.cfg
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone III FPGA
+# see Cyclone III Device Handbook
+# Table 12-2: Device IDCODE for Cyclone III Device Family
+
+#EP3C5     0x020f10dd
+#EP3C10    0x020f10dd
+#EP3C16    0x020f20dd
+#EP3C25    0x020f30dd
+#EP3C40    0x020f40dd
+#EP3C55    0x020f50dd
+#EP3C80    0x020f60dd
+#EP3C120   0x020f70dd
+#Cyclone III LS
+#EP3CLS70  0x027010dd
+#EP3CLS100 0x027000dd
+#EP3CLS150 0x027030dd
+#EP3CLS200 0x027020dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiii
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x020f10dd -expected-id 0x020f20dd \
+  -expected-id 0x020f30dd -expected-id 0x020f40dd \
+  -expected-id 0x020f50dd -expected-id 0x020f60dd \
+  -expected-id 0x020f70dd -expected-id 0x027010dd \
+  -expected-id 0x027000dd -expected-id 0x027030dd \
+  -expected-id 0x027020dd
+
+pld device intel $_CHIPNAME.tap cycloneiii
diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg
new file mode 100644
index 0000000..59243cf
--- /dev/null
+++ b/tcl/fpga/altera-cycloneiv.cfg
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone IV FPGA
+# see Cyclone IV Device Handbook
+# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
+
+#EP4CE6       0x020f10dd
+#EP4CE10      0x020f10dd
+#EP4CE15      0x020f20dd
+#EP4CE22      0x020f30dd
+#EP4CE30      0x020f40dd
+#EP4CE40      0x020f40dd
+#EP4CE55      0x020f50dd
+#EP4CE75      0x020f60dd
+#EP4CE115     0x020f70dd
+#EP4CGX15     0x028010dd
+#EP4CGX22     0x028120dd
+#EP4CGX30 (3) 0x028020dd
+#EP4CGX30 (4) 0x028230dd
+#EP4CGX50     0x028130dd
+#EP4CGX75     0x028030dd
+#EP4CGX110    0x028140dd
+#EP4CGX150    0x028040dd
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cycloneiv
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x020f10dd -expected-id 0x020f20dd \
+  -expected-id 0x020f30dd -expected-id 0x020f40dd \
+  -expected-id 0x020f50dd -expected-id 0x020f60dd \
+  -expected-id 0x020f70dd -expected-id 0x028010dd \
+  -expected-id 0x028120dd -expected-id 0x028020dd \
+  -expected-id 0x028230dd -expected-id 0x028130dd \
+  -expected-id 0x028030dd -expected-id 0x028140dd \
+  -expected-id 0x028040dd
+
+pld device intel $_CHIPNAME.tap cycloneiv
diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg
new file mode 100644
index 0000000..1e9c9c4
--- /dev/null
+++ b/tcl/fpga/altera-cyclonev.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel Cyclone 5 FPGA
+# see Cyclone V Device Handbook
+# Table 9-1: IDCODE Information for Cyclone V Devices
+
+#5CEA2 0x02b150dd
+#5CEA4 0x02b050dd
+#5CEA5 0x02b220dd
+#5CEA7 0x02b130dd
+#5CEA9 0x02b140dd
+#5CGXC3 0x02b010dd
+#5CGXC4 0x02b120dd
+#5CGXC5 0x02b020dd
+#5CGXC7 0x02b030dd
+#5CGXC9 0x02b040dd
+#5CGTD5 0x02b020dd
+#5CGTD7 0x02b030dd
+#5CGTD9 0x02b040dd
+#5CSEA2 0x02d110dd
+#5CSEA4 0x02d010dd
+#5CSEA5 0x02d120dd
+#5CSEA6 0x02d020dd
+#5CSXC2 0x02d110dd
+#5CSXC4 0x02d010dd
+#5CSXC5 0x02d120dd
+#5CSXC6 0x02d020dd
+#5CSTD5 0x02d120dd
+#5CSTD6 0x02d020dd
+
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME cyclonev
+}
+
+jtag newtap $_CHIPNAME tap -irlen 10 \
+  -expected-id 0x02b150dd -expected-id 0x02b050dd \
+  -expected-id 0x02b220dd -expected-id 0x02b130dd \
+  -expected-id 0x02b140dd -expected-id 0x02b010dd \
+  -expected-id 0x02b120dd -expected-id 0x02b020dd \
+  -expected-id 0x02b030dd -expected-id 0x02b040dd \
+  -expected-id 0x02d110dd -expected-id 0x02d010dd \
+  -expected-id 0x02d120dd -expected-id 0x02d020dd
+
+pld device intel $_CHIPNAME.tap cyclonev
diff --git a/tcl/fpga/altera-ep3c10.cfg b/tcl/fpga/altera-ep3c10.cfg
index 7c231f9..d7a92d7 100644
--- a/tcl/fpga/altera-ep3c10.cfg
+++ b/tcl/fpga/altera-ep3c10.cfg
@@ -1,6 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
-# Altera Cyclone III EP3C10
-# see Cyclone III Device Handbook, Volume 1;
-# Table 14–5. 32-Bit Cyclone III Device IDCODE
-jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10
+# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg
+echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg"
+
+#just to be backward compatible:
+#tap will be ep3c10.tap instead of cycloneiii.tap:
+set CHIPNAME ep3c10
+source [find fpga/altera-cycloneiii.cfg]