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| author | Lorenz Brun <lorenz@brun.one> | 2022-12-24 03:56:22 +0100 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-06-10 17:11:46 +0000 |
| commit | 63f4e7c72a27fb828fe1be3003be6a94519e1c12 (patch) | |
| tree | a975fad6a1b3d70a28a61ec16ee5d7ec96a7d668 /tcl | |
| parent | d8c9f66d25cde09570e4f87e354216470b72de7e (diff) | |
| download | riscv-openocd-63f4e7c72a27fb828fe1be3003be6a94519e1c12.zip riscv-openocd-63f4e7c72a27fb828fe1be3003be6a94519e1c12.tar.gz riscv-openocd-63f4e7c72a27fb828fe1be3003be6a94519e1c12.tar.bz2 | |
target/ti-cjtag: make switching to JTAG more reliable
The current cJTAG to JTAG switching commands for TI chips are not
particularly reliable, especially on chips with accurate timing.
On a Raspberry Pi the existing sequence has (depending on cabling and
chip) a ~50% chance of working, on a much better-behaved FT2232H
it doesn't manage to enable full JTAG at all.
This change runs a bunch of test-idle cycles before actually attempting
to switch to full JTAG. This makes the switch reliable even at high
clock speeds (>100kHz) and from precise sources like the FT2232H.
Change-Id: I9293e884bf3e9606d529756ae4483b844d3c39db
Reported-by: Phil Wiggum <p1mail2015@mail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/375/
Signed-off-by: Lorenz Brun <lorenz@brun.one>
Reviewed-on: https://review.openocd.org/c/openocd/+/7419
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/ti-cjtag.cfg | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti-cjtag.cfg index d5e13e2..97111f1 100644 --- a/tcl/target/ti-cjtag.cfg +++ b/tcl/target/ti-cjtag.cfg @@ -5,6 +5,7 @@ # Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information. proc ti_cjtag_to_4pin_jtag {jrc} { # Bypass + runtest 20 irscan $jrc 0x3f -endstate RUN/IDLE # Two zero bit scans and a one bit drshift pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE |