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| author | Tarek BOCHKATI <tarek.bouchkati@gmail.com> | 2021-12-03 12:58:33 +0100 |
|---|---|---|
| committer | Tomas Vanek <vanekt@fbl.cz> | 2023-05-24 05:28:09 +0000 |
| commit | 4defa3b1e323b7f7287d8e046b2c97ad4a749f87 (patch) | |
| tree | f5afcc6e039516c73e28588e78707a5ef793e925 /tcl | |
| parent | 5c46a5de49f5dd14227b9444a5815eaaadd7ceb4 (diff) | |
| download | riscv-openocd-4defa3b1e323b7f7287d8e046b2c97ad4a749f87.zip riscv-openocd-4defa3b1e323b7f7287d8e046b2c97ad4a749f87.tar.gz riscv-openocd-4defa3b1e323b7f7287d8e046b2c97ad4a749f87.tar.bz2 | |
flash/stm32l4x: support STM32C0x devices
this new STM32 series family introduces 2 devices:
STM32C011xx (0x443) and STM32C031xx (0x453)
both devices have 32 Kbytes single flash bank.
Change-Id: I4e890789e44e3b174c0e9c0e1068383ecdbb865f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6874
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/stm32c0x.cfg | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/tcl/target/stm32c0x.cfg b/tcl/target/stm32c0x.cfg new file mode 100644 index 0000000..d015120 --- /dev/null +++ b/tcl/target/stm32c0x.cfg @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for stm32c0x family +# +# stm32c0 devices support SWD transports only. +# + +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32c0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 6kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1800 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # SWD IDCODE (single drop, arm) + set _CPUTAPID 0x0bc11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME +flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME + +# reasonable default +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable DBGMCU clock + # RCC_APB1ENR |= DBGMCUEN + mmw 0x4002103C 0x08000000 0 + + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP + mmw 0x40015804 0x00000006 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP + mmw 0x40015808 0x00001800 0 +} |