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| author | Nishanth Menon <nm@ti.com> | 2021-10-01 23:18:09 -0500 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2022-03-12 09:40:28 +0000 |
| commit | 4ddca7dd7186a908397570a25f7ad7454bab3a20 (patch) | |
| tree | 091a7da077a0d58da14fa9d2e2f8cd9fbea9b154 /tcl | |
| parent | 77b02b89ae689867bb38e11d3fa6ff59c8d22357 (diff) | |
| download | riscv-openocd-4ddca7dd7186a908397570a25f7ad7454bab3a20.zip riscv-openocd-4ddca7dd7186a908397570a25f7ad7454bab3a20.tar.gz riscv-openocd-4ddca7dd7186a908397570a25f7ad7454bab3a20.tar.bz2 | |
tcl/target/ti_k3: Rename m4 target as general purpose mcu
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Diffstat (limited to 'tcl')
| -rw-r--r-- | tcl/target/ti_k3.cfg | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg index ee4a5c8..e397d22 100644 --- a/tcl/target/ti_k3.cfg +++ b/tcl/target/ti_k3.cfg @@ -43,13 +43,13 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000} set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000} set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000} -# Finally an M4F +# Finally an General Purpose(GP) MCU set CM4_CTIBASE {0x20001000} -# M4 may be present on some very few SoCs -set _mcu_m4_cores 0 -# M4 power-ap unlock offsets -set _m4_ap_unlock_offsets {0xf0 0x60} +# General Purpose MCU (M4) may be present on some very few SoCs +set _gp_mcu_cores 0 +# General Purpose MCU power-ap unlock offsets +set _gp_mcu_ap_unlock_offsets {0xf0 0x60} # Set configuration overrides for each SOC switch $_soc { @@ -95,7 +95,7 @@ switch $_soc { set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000} # M4 processor - set _mcu_m4_cores 1 + set _gp_mcu_cores 1 } j721e { set _CHIPNAME j721e @@ -246,22 +246,22 @@ if { $_main1_r5_cores != 0 } { } } -if { $_mcu_m4_cores != 0 } { - cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] - target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine - $_TARGETNAME.m4 configure -event reset-assert { } +if { $_gp_mcu_cores != 0 } { + cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0] + target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine + $_TARGETNAME.gp_mcu configure -event reset-assert { } - proc m4_up {} { - # To access M4, we need to enable the JTAG access for the same. + proc gp_mcu_up {} { + # To access GP MCU, we need to enable the JTAG access for the same. # Ensure Power-AP unlocked - $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000 - $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098 + $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000 + $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098 - $::_TARGETNAME.m4 arp_examine + $::_TARGETNAME.gp_mcu arp_examine } - $_TARGETNAME.m4 configure -event gdb-attach { - m4_up + $_TARGETNAME.gp_mcu configure -event gdb-attach { + gp_mcu_up # gdb-attach default rule halt 1000 } |