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authorTim Newsome <tim@sifive.com>2020-07-02 15:22:47 -0700
committerGitHub <noreply@github.com>2020-07-02 15:22:47 -0700
commitbbfc666eba84f7133510fa0c5cb1d2d9e7a49bce (patch)
tree2d48f82b97b897c234cabd70511bd175c9b44798 /tcl/target/omapl138.cfg
parentb50b8da476790fa5a1a0935d4837d2128a797db3 (diff)
parent7a52af41c1212acb922129b4b6558c220920dd38 (diff)
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Merge pull request #494 from riscv/from_upstream
Get changes from upstream
Diffstat (limited to 'tcl/target/omapl138.cfg')
-rw-r--r--tcl/target/omapl138.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/omapl138.cfg b/tcl/target/omapl138.cfg
index fd9ff4c..30cf23c 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/omapl138.cfg
@@ -52,8 +52,8 @@ $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable