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author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-11-14 12:23:24 +0100 |
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committer | Paul Fertser <fercerpav@gmail.com> | 2017-02-24 09:12:37 +0000 |
commit | 06ba5492df66e997eafe294fced505b11e67f2fc (patch) | |
tree | ebc6f0594a79f061d65cad9951a09965f148955b /src | |
parent | f988f5960450cf9e8c456bf8e3b4d2008e35a207 (diff) | |
download | riscv-openocd-06ba5492df66e997eafe294fced505b11e67f2fc.zip riscv-openocd-06ba5492df66e997eafe294fced505b11e67f2fc.tar.gz riscv-openocd-06ba5492df66e997eafe294fced505b11e67f2fc.tar.bz2 |
aarch64: remove mrs/msr functions from struct arm
No longer needed, no users.
Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3983
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/target/arm.h | 12 | ||||
-rw-r--r-- | src/target/armv8_dpm.c | 58 |
2 files changed, 0 insertions, 70 deletions
diff --git a/src/target/arm.h b/src/target/arm.h index e5e336d..d63ead2 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -189,18 +189,6 @@ struct arm { uint32_t CRn, uint32_t CRm, uint32_t value); - /** Read coprocessor register. */ - int (*mrs)(struct target *target, uint32_t op0, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t *value); - - /** Write coprocessor register. */ - int (*msr)(struct target *target, uint32_t cpnum, - uint32_t op1, uint32_t op2, - uint32_t CRn, uint32_t CRm, - uint32_t value); - void *arch_info; /** For targets conforming to ARM Debug Interface v5, diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index b06e456..acfd1bc 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -551,62 +551,6 @@ static int dpmv8_mcr(struct target *target, int cpnum, return retval; } -static int dpmv8_mrs(struct target *target, uint32_t op0, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t *value) -{ - struct arm *arm = target_to_arm(target); - struct arm_dpm *dpm = arm->dpm; - int retval; - uint32_t op_code; - - retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - return retval; - op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\ - (CRm & 0xF) << 8 | (op2 & 0x7) << 5); - op_code >>= 5; - LOG_DEBUG("MRS p%d, %d, r0, c%d, c%d, %d", (int)op0, - (int) op1, (int) CRn, - (int) CRm, (int) op2); - /* read coprocessor register into R0; return via DCC */ - retval = dpm->instr_read_data_r0(dpm, - ARMV8_MRS(op_code, 0), - value); - - /* (void) */ dpm->finish(dpm); - return retval; -} - -static int dpmv8_msr(struct target *target, uint32_t op0, - uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, - uint32_t value) -{ - struct arm *arm = target_to_arm(target); - struct arm_dpm *dpm = arm->dpm; - int retval; - uint32_t op_code; - - retval = dpm->prepare(dpm); - if (retval != ERROR_OK) - return retval; - - op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\ - (CRm & 0xF) << 8 | (op2 & 0x7) << 5); - op_code >>= 5; - LOG_DEBUG("MSR p%d, %d, r0, c%d, c%d, %d", (int)op0, - (int) op1, (int) CRn, - (int) CRm, (int) op2); - - /* read DCC into r0; then write coprocessor register from R0 */ - retval = dpm->instr_write_data_r0(dpm, - ARMV8_MSR_GP(op_code, 0), - value); - - /* (void) */ dpm->finish(dpm); - return retval; -} - /*----------------------------------------------------------------------*/ /* @@ -1449,8 +1393,6 @@ int armv8_dpm_setup(struct arm_dpm *dpm) /* coprocessor access setup */ arm->mrc = dpmv8_mrc; arm->mcr = dpmv8_mcr; - arm->mrs = dpmv8_mrs; - arm->msr = dpmv8_msr; dpm->prepare = dpmv8_dpm_prepare; dpm->finish = dpmv8_dpm_finish; |