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| author | Tim Newsome <tim@sifive.com> | 2020-02-14 14:54:05 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-14 14:54:05 -0800 |
| commit | 95462a8a35556259bd4555362f5367f8b48012f1 (patch) | |
| tree | 08498c249fe1c22a6cdb54dd2e2743b2af450587 /src/target/riscv/gdb_regs.h | |
| parent | 7cb8843794a258380b7c37509e5c693977675b2a (diff) | |
| download | riscv-openocd-95462a8a35556259bd4555362f5367f8b48012f1.zip riscv-openocd-95462a8a35556259bd4555362f5367f8b48012f1.tar.gz riscv-openocd-95462a8a35556259bd4555362f5367f8b48012f1.tar.bz2 | |
Add support for vector register access (#448)
* WIP
Change-Id: I0264a73b7f7d2ce89cc0b80692dbf81d9cdcc2fd
* Reading v* registers appears to work.
Can't really test it though, because gdb doesn't print them right.
Change-Id: I8d66339371c564a493d32f15c3d114b738a455c5
* Total hack to communicate registers to gdb.
Change-Id: Id06c819675f2a5bcaf751e322d95a7d71c633765
* Implement writing vector registers.
Fixed reading vector registers.
Change-Id: I8f06aa5ee5020b3213a4f68644c205c9d6b9d214
* Show gdb the actual size of the vector registers.
This length may be different per hart.
Change-Id: I92e95383da82ee7a5c995822a53d51b1ea933493
* Remove outdated todo comment.
Change-Id: Ic9158b002858f0d15a6452773b095aa5f4501128
* Removed TODO comment.
Filed #449 to track this.
Change-Id: I5277b19e545df2024f34cda39158ddf7d0d89d47
* Nicely handle some errors reading/writing V regs.
Change-Id: Ia7bb63a5f9433d9f7b46496b2c0994864cfc4a09
Diffstat (limited to 'src/target/riscv/gdb_regs.h')
| -rw-r--r-- | src/target/riscv/gdb_regs.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/target/riscv/gdb_regs.h b/src/target/riscv/gdb_regs.h index 04f8756..b118b7a 100644 --- a/src/target/riscv/gdb_regs.h +++ b/src/target/riscv/gdb_regs.h @@ -76,6 +76,12 @@ enum gdb_regno { GDB_REGNO_FT11, GDB_REGNO_FPR31 = GDB_REGNO_FT11, GDB_REGNO_CSR0 = 65, + GDB_REGNO_VSTART = CSR_VSTART + GDB_REGNO_CSR0, + GDB_REGNO_VXSAT = CSR_VXSAT + GDB_REGNO_CSR0, + GDB_REGNO_VXRM = CSR_VXRM + GDB_REGNO_CSR0, + GDB_REGNO_VLENB = CSR_VLENB + GDB_REGNO_CSR0, + GDB_REGNO_VL = CSR_VL + GDB_REGNO_CSR0, + GDB_REGNO_VTYPE = CSR_VTYPE + GDB_REGNO_CSR0, GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0, GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0, GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0, @@ -89,6 +95,18 @@ enum gdb_regno { GDB_REGNO_SATP = CSR_SATP + GDB_REGNO_CSR0, GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095, GDB_REGNO_PRIV = 4161, + /* It's still undecided what register numbers GDB will actually use for + * these. See + * https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/7lQYiTUN9Ms/gTxGhzaYBQAJ + */ + GDB_REGNO_V0, GDB_REGNO_V1, GDB_REGNO_V2, GDB_REGNO_V3, + GDB_REGNO_V4, GDB_REGNO_V5, GDB_REGNO_V6, GDB_REGNO_V7, + GDB_REGNO_V8, GDB_REGNO_V9, GDB_REGNO_V10, GDB_REGNO_V11, + GDB_REGNO_V12, GDB_REGNO_V13, GDB_REGNO_V14, GDB_REGNO_V15, + GDB_REGNO_V16, GDB_REGNO_V17, GDB_REGNO_V18, GDB_REGNO_V19, + GDB_REGNO_V20, GDB_REGNO_V21, GDB_REGNO_V22, GDB_REGNO_V23, + GDB_REGNO_V24, GDB_REGNO_V25, GDB_REGNO_V26, GDB_REGNO_V27, + GDB_REGNO_V28, GDB_REGNO_V29, GDB_REGNO_V30, GDB_REGNO_V31, GDB_REGNO_COUNT }; |