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author | Kirill Radkin <kirill.radkin@syntacore.com> | 2023-10-11 16:15:44 +0300 |
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committer | Kirill Radkin <kirill.radkin@syntacore.com> | 2023-12-07 20:59:10 +0300 |
commit | 84e6a4e6171cd41154d36e9226560571fcd8b5cd (patch) | |
tree | b5c2805a33adae9dcf8f9c7313064ad34c989ae3 /src/target/riscv/debug_defines.c | |
parent | 7c94814221138cdf674af6266bc5e23b47eeb561 (diff) | |
download | riscv-openocd-84e6a4e6171cd41154d36e9226560571fcd8b5cd.zip riscv-openocd-84e6a4e6171cd41154d36e9226560571fcd8b5cd.tar.gz riscv-openocd-84e6a4e6171cd41154d36e9226560571fcd8b5cd.tar.bz2 |
Update riscv/debug_defines (to sync with riscv-debug-spec:40b9a05)
Change-Id: Ie969866d1de83360a5f45e96e22108b58b8aa02f
Signed-off-by: Kirill Radkin <kirill.radkin@syntacore.com>
Diffstat (limited to 'src/target/riscv/debug_defines.c')
-rw-r--r-- | src/target/riscv/debug_defines.c | 576 |
1 files changed, 105 insertions, 471 deletions
diff --git a/src/target/riscv/debug_defines.c b/src/target/riscv/debug_defines.c index da20e19..d514c6e 100644 --- a/src/target/riscv/debug_defines.c +++ b/src/target/riscv/debug_defines.c @@ -1,6 +1,6 @@ /* * This file is auto-generated by running 'make debug_defines' in - * https://github.com/riscv/riscv-debug-spec/ (f546ddf) + * https://github.com/riscv/riscv-debug-spec/ (40b9a05) */ #include "debug_defines.h" @@ -63,15 +63,15 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_1(riscv_debug_reg_ctx_t conte } static const char *dtm_dtmcs_errinfo_values[8] = { - [0] = "not implemented", - [1] = "dmi error", - [2] = "communication error", - [3] = "device error", + [0] = "not_implemented", + [1] = "dmi_error", + [2] = "communication_error", + [3] = "device_error", [4] = "unknown" }; static const char *dtm_dtmcs_version_values[16] = { - [0] = "0.11", - [1] = "1.0", + [0] = "0_11", + [1] = "1_0", [15] = "custom" }; static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t context) @@ -219,32 +219,32 @@ static riscv_debug_reg_field_list_t dtm_dmi_get_op(riscv_debug_reg_ctx_t context static const char *csr_dcsr_debugver_values[16] = { [0] = "none", - [4] = "1.0", + [4] = "1_0", [15] = "custom" }; static const char *csr_dcsr_ebreakvs_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreakvu_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreakm_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreaks_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_ebreaku_values[2] = { [0] = "exception", - [1] = "debug mode" + [1] = "debug_mode" }; static const char *csr_dcsr_stepie_values[2] = { - [0] = "interrupts disabled", - [1] = "interrupts enabled" + [0] = "interrupts_disabled", + [1] = "interrupts_enabled" }; static const char *csr_dcsr_stopcount_values[2] = { [0] = "normal", @@ -491,6 +491,36 @@ static riscv_debug_reg_field_list_t csr_dpc_get_dpc(riscv_debug_reg_ctx_t contex return result; } +static riscv_debug_reg_field_list_t csr_dscratch0_get_dscratch0(riscv_debug_reg_ctx_t context) +{ + assert(context.DXLEN.is_set); + riscv_debug_reg_field_list_t result = { + .field = { + .name = "dscratch0", + .lsb = 0, + .msb = (context.DXLEN.value + -1), + .values = NULL + }, + .get_next = NULL + }; + return result; +} + +static riscv_debug_reg_field_list_t csr_dscratch1_get_dscratch1(riscv_debug_reg_ctx_t context) +{ + assert(context.DXLEN.is_set); + riscv_debug_reg_field_list_t result = { + .field = { + .name = "dscratch1", + .lsb = 0, + .msb = (context.DXLEN.value + -1), + .values = NULL + }, + .get_next = NULL + }; + return result; +} + static riscv_debug_reg_field_list_t csr_tselect_get_index(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); @@ -660,12 +690,12 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t c return result; } -static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ctx_t context) +static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); riscv_debug_reg_field_list_t result = { .field = { - .name = "hcontext", + .name = "data", .lsb = 0, .msb = (context.XLEN.value + -1), .values = NULL @@ -675,12 +705,12 @@ static riscv_debug_reg_field_list_t csr_hcontext_get_hcontext(riscv_debug_reg_ct return result; } -static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context) +static riscv_debug_reg_field_list_t csr_mcontext_get_hcontext(riscv_debug_reg_ctx_t context) { assert(context.XLEN.is_set); riscv_debug_reg_field_list_t result = { .field = { - .name = "data", + .name = "hcontext", .lsb = 0, .msb = (context.XLEN.value + -1), .values = NULL @@ -701,10 +731,10 @@ static const char *csr_mcontrol_timing_values[2] = { static const char *csr_mcontrol_sizelo_values[4] = {}; static const char *csr_mcontrol_action_values[16] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -717,12 +747,12 @@ static const char *csr_mcontrol_match_values[16] = { [1] = "napot", [2] = "ge", [3] = "lt", - [4] = "mask low", - [5] = "mask high", - [8] = "not equal", - [9] = "not napot", - [12] = "not mask low", - [13] = "not mask high" + [4] = "mask_low", + [5] = "mask_high", + [8] = "not_equal", + [9] = "not_napot", + [12] = "not_mask_low", + [13] = "not_mask_high" }; static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t context) { @@ -985,10 +1015,10 @@ static const char *csr_mcontrol6_size_values[8] = { }; static const char *csr_mcontrol6_action_values[16] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1001,12 +1031,12 @@ static const char *csr_mcontrol6_match_values[16] = { [1] = "napot", [2] = "ge", [3] = "lt", - [4] = "mask low", - [5] = "mask high", - [8] = "not equal", - [9] = "not napot", - [12] = "not mask low", - [13] = "not mask high" + [4] = "mask_low", + [5] = "mask_high", + [8] = "not_equal", + [9] = "not_napot", + [12] = "not_mask_low", + [13] = "not_mask_high" }; static const char *csr_mcontrol6_uncertainen_values[2] = { [0] = "disabled", @@ -1282,10 +1312,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_load(riscv_debug_reg_ctx_t static const char *csr_icount_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1447,10 +1477,10 @@ static riscv_debug_reg_field_list_t csr_icount_get_action(riscv_debug_reg_ctx_t static const char *csr_itrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1599,10 +1629,10 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_action(riscv_debug_reg_ctx_ static const char *csr_etrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -1737,10 +1767,10 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_action(riscv_debug_reg_ctx_ static const char *csr_tmexttrigger_action_values[64] = { [0] = "breakpoint", - [1] = "debug mode", - [2] = "trace on", - [3] = "trace off", - [4] = "trace notify", + [1] = "debug_mode", + [2] = "trace_on", + [3] = "trace_off", + [4] = "trace_notify", [8] = "external0", [9] = "external1" }; @@ -2002,9 +2032,9 @@ static const char *dm_dmstatus_confstrptrvalid_values[2] = { }; static const char *dm_dmstatus_version_values[16] = { [0] = "none", - [1] = "0.11", - [2] = "0.13", - [3] = "1.0", + [1] = "0_11", + [2] = "0_13", + [3] = "1_0", [15] = "custom" }; static riscv_debug_reg_field_list_t dm_dmstatus_get_allhalted(riscv_debug_reg_ctx_t context) @@ -2592,15 +2622,15 @@ static const char *dm_abstractcs_busy_values[2] = { [1] = "busy" }; static const char *dm_abstractcs_relaxedpriv_values[2] = { - [0] = "full checks", - [1] = "relaxed checks" + [0] = "full_checks", + [1] = "relaxed_checks" }; static const char *dm_abstractcs_cmderr_values[8] = { [0] = "none", [1] = "busy", - [2] = "not supported", + [2] = "not_supported", [3] = "exception", - [4] = "halt/resume", + [4] = "halt_resume", [5] = "bus", [6] = "reserved", [7] = "other" @@ -2979,7 +3009,7 @@ static riscv_debug_reg_field_list_t dm_haltsum3_get_haltsum3(riscv_debug_reg_ctx static const char *dm_sbcs_sbversion_values[8] = { [0] = "legacy", - [1] = "1.0" + [1] = "1_0" }; static const char *dm_sbcs_sbaccess_values[8] = { [0] = "8bit", @@ -3578,398 +3608,6 @@ static riscv_debug_reg_field_list_t virt_priv_get_prv(riscv_debug_reg_ctx_t cont return result; } -static riscv_debug_reg_field_list_t dmi_sercs_get_full3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full3", - .lsb = 9, - .msb = 9, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error2", - .lsb = 8, - .msb = 8, - .values = NULL - }, - .get_next = dmi_sercs_get_full3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid2", - .lsb = 7, - .msb = 7, - .values = NULL - }, - .get_next = dmi_sercs_get_error2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full2(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full2", - .lsb = 6, - .msb = 6, - .values = NULL - }, - .get_next = dmi_sercs_get_valid2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error1", - .lsb = 5, - .msb = 5, - .values = NULL - }, - .get_next = dmi_sercs_get_full2 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid1", - .lsb = 4, - .msb = 4, - .values = NULL - }, - .get_next = dmi_sercs_get_error1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full1(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full1", - .lsb = 3, - .msb = 3, - .values = NULL - }, - .get_next = dmi_sercs_get_valid1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_serialcount(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "serialcount", - .lsb = 0x1c, - .msb = 0x1f, - .values = NULL - }, - .get_next = dmi_sercs_get_full1 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_serial(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "serial", - .lsb = 0x18, - .msb = 0x1a, - .values = NULL - }, - .get_next = dmi_sercs_get_serialcount - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error7", - .lsb = 0x17, - .msb = 0x17, - .values = NULL - }, - .get_next = dmi_sercs_get_serial - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid7", - .lsb = 0x16, - .msb = 0x16, - .values = NULL - }, - .get_next = dmi_sercs_get_error7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full7(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full7", - .lsb = 0x15, - .msb = 0x15, - .values = NULL - }, - .get_next = dmi_sercs_get_valid7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error6", - .lsb = 0x14, - .msb = 0x14, - .values = NULL - }, - .get_next = dmi_sercs_get_full7 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error0", - .lsb = 2, - .msb = 2, - .values = NULL - }, - .get_next = dmi_sercs_get_error6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid6", - .lsb = 0x13, - .msb = 0x13, - .values = NULL - }, - .get_next = dmi_sercs_get_error0 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full6(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full6", - .lsb = 0x12, - .msb = 0x12, - .values = NULL - }, - .get_next = dmi_sercs_get_valid6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error5", - .lsb = 0x11, - .msb = 0x11, - .values = NULL - }, - .get_next = dmi_sercs_get_full6 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid5", - .lsb = 0x10, - .msb = 0x10, - .values = NULL - }, - .get_next = dmi_sercs_get_error5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full5(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full5", - .lsb = 0xf, - .msb = 0xf, - .values = NULL - }, - .get_next = dmi_sercs_get_valid5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error4", - .lsb = 0xe, - .msb = 0xe, - .values = NULL - }, - .get_next = dmi_sercs_get_full5 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid4", - .lsb = 0xd, - .msb = 0xd, - .values = NULL - }, - .get_next = dmi_sercs_get_error4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full4(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full4", - .lsb = 0xc, - .msb = 0xc, - .values = NULL - }, - .get_next = dmi_sercs_get_valid4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_error3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "error3", - .lsb = 0xb, - .msb = 0xb, - .values = NULL - }, - .get_next = dmi_sercs_get_full4 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid3(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid3", - .lsb = 0xa, - .msb = 0xa, - .values = NULL - }, - .get_next = dmi_sercs_get_error3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_valid0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "valid0", - .lsb = 1, - .msb = 1, - .values = NULL - }, - .get_next = dmi_sercs_get_valid3 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sercs_get_full0(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "full0", - .lsb = 0, - .msb = 0, - .values = NULL - }, - .get_next = dmi_sercs_get_valid0 - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_sertx_get_data(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "data", - .lsb = 0, - .msb = 0x1f, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - -static riscv_debug_reg_field_list_t dmi_serrx_get_data(riscv_debug_reg_ctx_t context) -{ - riscv_debug_reg_field_list_t result = { - .field = { - .name = "data", - .lsb = 0, - .msb = 0x1f, - .values = NULL - }, - .get_next = NULL - }; - return result; -} - riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg_ordinal) { static const riscv_debug_reg_info_t debug_reg_info[] = { @@ -3997,6 +3635,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "dpc", .get_fields_head = csr_dpc_get_dpc }, + [CSR_DSCRATCH0_ORDINAL] = { + .name = "dscratch0", + .get_fields_head = csr_dscratch0_get_dscratch0 + }, + [CSR_DSCRATCH1_ORDINAL] = { + .name = "dscratch1", + .get_fields_head = csr_dscratch1_get_dscratch1 + }, [CSR_TSELECT_ORDINAL] = { .name = "tselect", .get_fields_head = csr_tselect_get_index @@ -4021,14 +3667,14 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "tcontrol", .get_fields_head = csr_tcontrol_get_mte }, - [CSR_HCONTEXT_ORDINAL] = { - .name = "hcontext", - .get_fields_head = csr_hcontext_get_hcontext - }, [CSR_SCONTEXT_ORDINAL] = { .name = "scontext", .get_fields_head = csr_scontext_get_data }, + [CSR_MCONTEXT_ORDINAL] = { + .name = "mcontext", + .get_fields_head = csr_mcontext_get_hcontext + }, [CSR_MCONTROL_ORDINAL] = { .name = "mcontrol", .get_fields_head = csr_mcontrol_get_load @@ -4201,18 +3847,6 @@ riscv_debug_reg_info_t get_riscv_debug_reg_info(enum riscv_debug_reg_ordinal reg .name = "priv", .get_fields_head = virt_priv_get_prv }, - [DMI_SERCS_ORDINAL] = { - .name = "sercs", - .get_fields_head = dmi_sercs_get_full0 - }, - [DMI_SERTX_ORDINAL] = { - .name = "sertx", - .get_fields_head = dmi_sertx_get_data - }, - [DMI_SERRX_ORDINAL] = { - .name = "serrx", - .get_fields_head = dmi_serrx_get_data - }, }; return debug_reg_info[reg_ordinal]; } |