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| author | Salvador Arroyo <sarroyofdez@yahoo.es> | 2017-05-07 11:58:25 +0200 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2017-05-08 18:03:28 +0100 |
| commit | 2279c23cdeaea05839a28ff3addf12b9b0f5357e (patch) | |
| tree | 29353f10f210a78ad26e7403ab48df04af95595e /src/target/mips32_pracc.h | |
| parent | 6012a87d4464cdbf65ba46cb5c98d6113b5d7aea (diff) | |
| download | riscv-openocd-2279c23cdeaea05839a28ff3addf12b9b0f5357e.zip riscv-openocd-2279c23cdeaea05839a28ff3addf12b9b0f5357e.tar.gz riscv-openocd-2279c23cdeaea05839a28ff3addf12b9b0f5357e.tar.bz2 | |
mips32, add support for micromips in debug mode
Micromips is 16bit oriented, branch and jumps are
16 bit based. The upper half 16bits of a 32bit instruction
with the major opcode, must go first in the instruction
stream, hence the SWAP16 macro and swap16 array function,
needed if the code is written as 32 bit word in little endian
cores. Endianess info added to ejtag_iinfo. Pointer to
ejtag_info and isa field added to pracc context.
MIPS32 code are renamed to MIPS32_ISA_...
To select the isa, the new code has an additional isa parameter
(1 for micromips, 0 for mips32).
In JR instruction the isa bit must be set to execute
micromips code.
The suffix u is added to the OP codes to avoid signed/unsigned
comparison errors and to make sure the right shift is
performed logically.
The isa in debug mode is updated in the poll function.
Code for miniprograms, in kernel mode, need to be converted.
CFI code only for mips32.
Change-Id: I79a8b637d49b0e2d92b6dd5eb5aa8aa0520bf938
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/4032
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'src/target/mips32_pracc.h')
| -rw-r--r-- | src/target/mips32_pracc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index e990f8d..fe9f814 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -40,6 +40,7 @@ #define UPPER16(uint32_t) (uint32_t >> 16) #define LOWER16(uint32_t) (uint32_t & 0xFFFF) #define NEG16(v) (((~(v)) + 1) & 0xFFFF) +#define SWAP16(v) ((LOWER16(v) << 16) | (UPPER16(v))) /*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/ #define PRACC_BLOCK 128 /* 1 Kbyte */ @@ -50,12 +51,15 @@ typedef struct { } pa_list; struct pracc_queue_info { + struct mips_ejtag *ejtag_info; + unsigned isa; int retval; int code_count; int store_count; int max_code; /* max intstructions with currently allocated memory */ pa_list *pracc_list; /* Code and store addresses at dmseg */ }; + void pracc_queue_init(struct pracc_queue_info *ctx); void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr); void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t data, bool optimize); @@ -108,4 +112,11 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info, int mips32_cp0_write(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel); +inline void pracc_swap16_array(struct mips_ejtag *ejtag_info, uint32_t *buf, int count) +{ + if (ejtag_info->isa && ejtag_info->endianness) + for (int i = 0; i != count; i++) + buf[i] = SWAP16(buf[i]); +} + #endif /* OPENOCD_TARGET_MIPS32_PRACC_H */ |