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author | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-01 21:47:45 -0800 |
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committer | David Brownell <dbrownell@users.sourceforge.net> | 2009-12-01 21:47:45 -0800 |
commit | 66ca84b58114ad73b5843f62f9f5fbead1126fca (patch) | |
tree | c154e6084a6ccc742d1ec8be002ffa187a8c61b5 /src/target/arm11.c | |
parent | 1c7d3d200c6f20d4bb689176373368cd497d797f (diff) | |
download | riscv-openocd-66ca84b58114ad73b5843f62f9f5fbead1126fca.zip riscv-openocd-66ca84b58114ad73b5843f62f9f5fbead1126fca.tar.gz riscv-openocd-66ca84b58114ad73b5843f62f9f5fbead1126fca.tar.bz2 |
ARM: core DPM support for watchpoints
This is a NOP unless the underlying core exposes two new methods, and
neither of the two cores using this (ARM11xx, Cortex-A8) do so yet.
This patch only updates those cores so they pass a flag saying whether
or not to update breakpoint and watchpoint status before resuming; and
removing some now-needless anti-segfault code from ARM11. Cortex-A8
didn't have that code ... yes, it segfaulted when setting watchpoints.
NOTE: this uses a slightly different strategy for setting/clearing
breakpoints than the ARM7/ARM9/etc code uses. It leaves them alone
unless it's *got* to change something, to speed halt/resume cycles
(including single stepping).
ALSO NOTE: this under-delivers for Cortex-A8, where regions with size
up to 2 GBytes can be watched ... it handles watchpoints which ARM11 can
also handle (size 1/2/4 bytes). Should get fixed later.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'src/target/arm11.c')
-rw-r--r-- | src/target/arm11.c | 35 |
1 files changed, 8 insertions, 27 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c index fd9b465..605e741 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -293,12 +293,11 @@ static int arm11_on_enter_debug_state(struct arm11_common *arm11) return ERROR_OK; } -/** Restore processor state - * - * This is called in preparation for the RESTART function. - * - */ -static int arm11_leave_debug_state(struct arm11_common *arm11) +/** + * Restore processor state. This is called in preparation for + * the RESTART function. + */ +static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp) { int retval; @@ -354,7 +353,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11) /* restore CPSR, PC, and R0 ... after flushing any modified * registers. */ - retval = arm_dpm_write_dirty_registers(&arm11->dpm); + retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp); register_cache_invalidate(arm11->arm.core_cache); @@ -598,7 +597,7 @@ static int arm11_resume(struct target *target, int current, arm11_sc7_set_vcr(arm11, arm11_vcr); } - arm11_leave_debug_state(arm11); + arm11_leave_debug_state(arm11, handle_breakpoints); arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); @@ -762,7 +761,7 @@ static int arm11_step(struct target *target, int current, R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE; - CHECK_RETVAL(arm11_leave_debug_state(arm11)); + CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints)); arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); @@ -1203,22 +1202,6 @@ static int arm11_remove_breakpoint(struct target *target, return ERROR_OK; } -static int arm11_add_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - -static int arm11_remove_watchpoint(struct target *target, - struct watchpoint *watchpoint) -{ - LOG_WARNING("Not implemented: %s", __func__); - - return ERROR_FAIL; -} - static int arm11_target_create(struct target *target, Jim_Interp *interp) { struct arm11_common *arm11; @@ -1605,8 +1588,6 @@ struct target_type arm11_target = { .add_breakpoint = arm11_add_breakpoint, .remove_breakpoint = arm11_remove_breakpoint, - .add_watchpoint = arm11_add_watchpoint, - .remove_watchpoint = arm11_remove_watchpoint, .run_algorithm = armv4_5_run_algorithm, |