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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2018-05-30 07:04:14 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2018-05-30 07:04:14 -0700 |
| commit | 6d9e69499f3f6810434c1eb5acf69d6275fddfd0 (patch) | |
| tree | d489b13d016ee24cc20c345d1665506a4966972f | |
| parent | 06bc6cccd4eb92192ab7c001c9b07c189a605970 (diff) | |
| download | riscv-openocd-6d9e69499f3f6810434c1eb5acf69d6275fddfd0.zip riscv-openocd-6d9e69499f3f6810434c1eb5acf69d6275fddfd0.tar.gz riscv-openocd-6d9e69499f3f6810434c1eb5acf69d6275fddfd0.tar.bz2 | |
Don't rely on the RTOS hartid for the register cache
| -rw-r--r-- | src/target/riscv/riscv.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 74f1c7e..1d83bad 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1755,8 +1755,7 @@ int riscv_set_current_hartid(struct target *target, int hartid) /* Avoid invalidating the register cache all the time. */ if (r->registers_initialized && (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) - && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target) - && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) { + && target->reg_cache->reg_list[GDB_REGNO_ZERO].size == (unsigned)riscv_xlen(target)) { return ERROR_OK; } else LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target)); |