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| author | Tim Newsome <tim@sifive.com> | 2017-10-18 11:27:28 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-10-18 11:47:15 -0700 |
| commit | 7edd9b17862570352c4c70729f2f141ec06f8325 (patch) | |
| tree | dc215359f04b240d23589164e0eab10763198f2e | |
| parent | a0623b2fa83eeeef91b83f193c98a1354d5963f9 (diff) | |
| download | riscv-openocd-7edd9b17862570352c4c70729f2f141ec06f8325.zip riscv-openocd-7edd9b17862570352c4c70729f2f141ec06f8325.tar.gz riscv-openocd-7edd9b17862570352c4c70729f2f141ec06f8325.tar.bz2 | |
Fix FPR access.
Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
| -rw-r--r-- | src/target/riscv/riscv-013.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 8e7a2f0..70531e9 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -767,9 +767,9 @@ static int register_write_direct(struct target *target, unsigned number, if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) { if (supports_extension(target, 'D') && riscv_xlen(target) >= 64) { - riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0)); + riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0)); } else { - riscv_program_insert(&program, fmv_x_s(S0, number - GDB_REGNO_FPR0)); + riscv_program_insert(&program, fmv_s_x(number - GDB_REGNO_FPR0, S0)); } } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { riscv_program_csrw(&program, S0, number); @@ -811,9 +811,9 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t // TODO: Possibly set F in mstatus. // TODO: Fully support D extension on RV32. if (supports_extension(target, 'D') && riscv_xlen(target) >= 64) { - riscv_program_insert(&program, fmv_d_x(number - GDB_REGNO_FPR0, S0)); + riscv_program_insert(&program, fmv_x_d(S0, number - GDB_REGNO_FPR0)); } else { - riscv_program_insert(&program, fmv_s_x(number - GDB_REGNO_FPR0, S0)); + riscv_program_insert(&program, fmv_x_s(S0, number - GDB_REGNO_FPR0)); } } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) { riscv_program_csrr(&program, S0, number); @@ -1086,9 +1086,12 @@ static int examine(struct target *target) r->xlen[i] = 32; } + r->misa = riscv_get_register_on_hart(target, i, GDB_REGNO_MISA); + /* Display this as early as possible to help people who are using * really slow simulators. */ - LOG_DEBUG(" hart %d: XLEN=%d", i, r->xlen[i]); + LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, i, r->xlen[i], + r->misa); } /* Then we check the number of triggers availiable to each hart. */ |