diff options
| author | Bohdan Tymkiv <bohdan200@gmail.com> | 2023-05-23 14:40:11 +0300 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-06-02 20:57:49 +0000 |
| commit | 72131e05e9337f1f950f604f5e07683e887ce3ab (patch) | |
| tree | 3b094031ff3f5fe83cce4926263ceee7ae69bd77 | |
| parent | 4a57f3ebb21db6b89b0ceb9df34d32157731ead2 (diff) | |
| download | riscv-openocd-72131e05e9337f1f950f604f5e07683e887ce3ab.zip riscv-openocd-72131e05e9337f1f950f604f5e07683e887ce3ab.tar.gz riscv-openocd-72131e05e9337f1f950f604f5e07683e887ce3ab.tar.bz2 | |
cortex_m: fix reading of DCB_DSCSR register
Value in the 'dscsr' variable is garbage until the DAP queue is run.
Postpone evaluation of the 'secure_state' variable. Reading the
core registers in between will execute the DAP queue.
Change-Id: I44959e882dbafb1b9779e813c3d13f3b3dbcd47f
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7693
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
| -rw-r--r-- | src/target/cortex_m.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 8e55014..ebc3bac 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -801,15 +801,11 @@ static int cortex_m_debug_entry(struct target *target) return retval; /* examine PE security state */ - bool secure_state = false; + uint32_t dscsr = 0; if (armv7m->arm.arch == ARM_ARCH_V8M) { - uint32_t dscsr; - retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr); if (retval != ERROR_OK) return retval; - - secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS; } /* Load all registers to arm.core_cache */ @@ -857,6 +853,7 @@ static int cortex_m_debug_entry(struct target *target) if (armv7m->exception_number) cortex_m_examine_exception_reason(target); + bool secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS; LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s", arm_mode_name(arm->core_mode), |