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| author | Tim Newsome <tim@sifive.com> | 2022-04-27 12:58:57 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-27 12:58:57 -0700 |
| commit | edcfcab8903afa96563a31852266b7bc265f32ee (patch) | |
| tree | bcba4085dbcc0f2f35210ba534d2ecadb074f11e | |
| parent | a6f32126846a4094c60c60b31393b9e1ab0b22fe (diff) | |
| download | riscv-openocd-edcfcab8903afa96563a31852266b7bc265f32ee.zip riscv-openocd-edcfcab8903afa96563a31852266b7bc265f32ee.tar.gz riscv-openocd-edcfcab8903afa96563a31852266b7bc265f32ee.tar.bz2 | |
Add trigger_hit field to riscv_info
Change-Id: If4e1b5c37da4ab9301d91f41ba4789662b677a29
| -rw-r--r-- | src/target/riscv/riscv.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 59680de..59fdb38 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -124,6 +124,10 @@ typedef struct { * target controls, while otherwise only a single hart is controlled. */ int trigger_unique_id[RISCV_MAX_HWBPS]; + /* The unique id of the trigger that caused the most recent halt. If the + * most recent halt was not caused by a trigger, then this is -1. */ + uint32_t trigger_hit; + /* The number of entries in the debug buffer. */ int debug_buffer_size; |