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| author | Tim Newsome <tim@sifive.com> | 2022-04-27 13:00:47 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-27 13:00:47 -0700 |
| commit | d67a5bf0645f099f1d6457e4007ddb22b38a744b (patch) | |
| tree | b973eecb348dc1707b405689be3f4c67369fa1c1 | |
| parent | 68e41dc1c8cc3815290a6997763f19a2dd52324a (diff) | |
| download | riscv-openocd-d67a5bf0645f099f1d6457e4007ddb22b38a744b.zip riscv-openocd-d67a5bf0645f099f1d6457e4007ddb22b38a744b.tar.gz riscv-openocd-d67a5bf0645f099f1d6457e4007ddb22b38a744b.tar.bz2 | |
During polling, check which trigger has `hit` set.
Change-Id: If226810ed930e5d7a2bab277a9f5b0f3ded86ffa
| -rw-r--r-- | src/target/riscv/riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index a03de6c..ee58381 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1252,11 +1252,15 @@ int riscv_flush_registers(struct target *target) /* Convert: RISC-V hart's halt reason --> OpenOCD's generic debug reason */ int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) { + RISCV_INFO(r); + r->trigger_hit = -1; switch (halt_reason) { case RISCV_HALT_BREAKPOINT: target->debug_reason = DBG_REASON_BREAKPOINT; break; case RISCV_HALT_TRIGGER: + if (riscv_hit_trigger_hit_bit(target, &r->trigger_hit) != ERROR_OK) + return ERROR_FAIL; target->debug_reason = DBG_REASON_WATCHPOINT; break; case RISCV_HALT_INTERRUPT: |