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| author | Tim Newsome <tim@sifive.com> | 2022-04-27 13:01:14 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-04-27 13:01:14 -0700 |
| commit | 73199226dfaf2df1c009509358c3a48fc3b0970d (patch) | |
| tree | 10d95e64c4a03e179e92436d6505e0c9797740c4 | |
| parent | d67a5bf0645f099f1d6457e4007ddb22b38a744b (diff) | |
| download | riscv-openocd-73199226dfaf2df1c009509358c3a48fc3b0970d.zip riscv-openocd-73199226dfaf2df1c009509358c3a48fc3b0970d.tar.gz riscv-openocd-73199226dfaf2df1c009509358c3a48fc3b0970d.tar.bz2 | |
Report some triggers as hardware breakpoints.
Instead of reporting them all as watchpoints.
Change-Id: If43d282a168f64f8fed6f659bcebbe2ef72f23e9
| -rw-r--r-- | src/target/riscv/riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index ee58381..26824a9 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1262,6 +1262,11 @@ int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason) if (riscv_hit_trigger_hit_bit(target, &r->trigger_hit) != ERROR_OK) return ERROR_FAIL; target->debug_reason = DBG_REASON_WATCHPOINT; + /* Check if we hit a hardware breakpoint. */ + for (struct breakpoint *bp = target->breakpoints; bp; bp = bp->next) { + if (bp->unique_id == r->trigger_hit) + target->debug_reason = DBG_REASON_BREAKPOINT; + } break; case RISCV_HALT_INTERRUPT: case RISCV_HALT_GROUP: |