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authorSean Anderson <sean.anderson@seco.com>2022-02-21 14:06:51 -0500
committerAntonio Borneo <borneo.antonio@gmail.com>2022-03-12 09:46:30 +0000
commit5b70c1f679755677c925b4e6dd2c3d8be4715717 (patch)
tree858d469bae55088d76168e6da271c988905f5ccc
parent1c22c5a82b248b7209fdc904e733b9fa29307c48 (diff)
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target: Add LS1046A
The LS1046A is a quad-core processor from NXP in the layerscape family. This SoC is a bit tricky to program: while the AArch64 CPUs are little-endian, most of the peripherals are big-endian. Care must be taken when interpreting memory reads/writes. This processor is in the same family as the ls1012a, so the setup is similar. If you use OpenOCD to attach early in the boot process, only the cpu0 may be available. Trying to halt other CPUs will fail. To avoid this, defer examination of cpus 1-3, and provide a core_up helper (like e.g. zynqmp). Signed-off-by: Sean Anderson <sean.anderson@seco.com> Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54 Reviewed-on: https://review.openocd.org/c/openocd/+/6854 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-rw-r--r--tcl/target/ls1046a.cfg56
1 files changed, 56 insertions, 0 deletions
diff --git a/tcl/target/ls1046a.cfg b/tcl/target/ls1046a.cfg
new file mode 100644
index 0000000..3d96a99
--- /dev/null
+++ b/tcl/target/ls1046a.cfg
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046A
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ls1046a
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+ set _SAP_TAPID $SAP_TAPID
+} else {
+ set _SAP_TAPID 0x06b3001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _CPU_BASE 0x80400000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < 4} {incr i} {
+ set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+ cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \
+ -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+ target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+ -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+ -coreid $i {*}[expr {$i ? {-defer-examine} : {-rtos hwthread} }]
+ lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big
+
+proc core_up { args } {
+ foreach core $args {
+ $::_CHIPNAME.cpu$core arp_examine
+ }
+}
+
+targets $_CHIPNAME.cpu0
+
+adapter speed 10000