tcl/target: update esp32.cfg to reference shared functions in the esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9181737d83eeba4e983b6a455b8a1523f2576dd2
Reviewed-on: https://review.openocd.org/c/openocd/+/7745
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins

1 files changed, 15 insertions, 79 deletions

diff --git a/tcl/target/esp32.cfg b/tcl/target/esp32.cfg
index f4c13aa..b30a170 100644
--- a/tcl/target/esp32.cfg
+++ b/tcl/target/esp32.cfg
@@ -1,99 +1,35 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32 only supports JTAG.
-transport select jtag
 
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x120034e5
-}
+# Target specific global variables
+set _CHIPNAME 					"esp32"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _FLASH_VOLTAGE 				3.3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG 	0x3ff5A004
 
 if { [info exists ESP32_ONLYCPU] } {
 	set _ONLYCPU $ESP32_ONLYCPU
-} else {
-	set _ONLYCPU 2
 }
 
 if { [info exists ESP32_FLASH_VOLTAGE] } {
 	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
-} else {
-	set _FLASH_VOLTAGE 3.3
-}
-
-set _CPU0NAME cpu0
-set _CPU1NAME cpu1
-set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
-set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
-
-jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
-if { $_ONLYCPU != 1 } {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
-} else {
-	jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
-}
-
-# PRO-CPU
-target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
-# APP-CPU
-if { $_ONLYCPU != 1 } {
-	target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
-	target smp $_TARGETNAME_0 $_TARGETNAME_1
-}
-
-$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE
-$_TARGETNAME_0 xtensa maskisr on
-$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
-
-$_TARGETNAME_0 configure -event gdb-attach {
-	$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-	# necessary to auto-probe flash bank when GDB is connected
-	halt 1000
-}
-
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event gdb-attach {
-		$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
-		# necessary to auto-probe flash bank when GDB is connected
-		halt 1000
-	}
-	$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
 }
 
-$_TARGETNAME_0 configure -event examine-end {
-    # Need to enable to set 'semihosting_basedir'
-    arm semihosting enable
-    arm semihosting_resexit enable
-    if { [info exists _SEMIHOST_BASEDIR] } {
-        if { $_SEMIHOST_BASEDIR != "" } {
-            arm semihosting_basedir $_SEMIHOST_BASEDIR
-        }
-    }
+proc esp32_memprot_is_enabled { } {
+	return 0
 }
 
-if { $_ONLYCPU != 1 } {
-	$_TARGETNAME_1 configure -event examine-end {
-		# Need to enable to set 'semihosting_basedir'
-		arm semihosting enable
-		arm semihosting_resexit enable
-		if { [info exists _SEMIHOST_BASEDIR] } {
-			if { $_SEMIHOST_BASEDIR != "" } {
-				arm semihosting_basedir $_SEMIHOST_BASEDIR
-			}
-		}
-	}
+proc esp32_soc_reset { } {
+	soft_reset_halt
 }
 
-gdb_breakpoint_override hard
+create_esp_target $_ESP_ARCH
 
 source [find target/xtensa-core-esp32.cfg]