tcl/target: update esp32c3.cfg to reference shared functions in the esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie3413d3149388b17bc0199409ce86d3eb7cf5ee2

2 files changed, 52 insertions, 65 deletions

diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg
index ecb9bdf..d266ad5 100644
--- a/tcl/target/esp32c3.cfg
+++ b/tcl/target/esp32c3.cfg
@@ -1,30 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32-C3 only supports JTAG.
-transport select jtag
 
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32c3
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x00005c25
-}
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x00005c25
+set _ESP_ARCH					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008844
 
-set _TARGETNAME $_CHIPNAME
-set _CPUNAME cpu
-set _TAPNAME $_CHIPNAME.$_CPUNAME
-
-jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
-
-proc esp32c3_wdt_disable { } {
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
     # Halt event can occur during config phase (before "init" is done).
     # Ignore it since mww commands don't work at that time.
     if { [string compare [command mode] config] == 0 } {
@@ -46,7 +36,9 @@ proc esp32c3_wdt_disable { } {
 
 # This is almost identical with the esp32c2_soc_reset.
 # Will be refactored with the other common settings.
-proc esp32c3_soc_reset { } {
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
     # This procedure does "digital system reset", i.e. resets
     # all the peripherals except for the RTC block.
     # It is called from reset-assert-post target event callback,
@@ -54,7 +46,7 @@ proc esp32c3_soc_reset { } {
     # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
     # temporarily take it out of reset. Save the dmcontrol state before
     # doing so.
-    riscv dmi_write 0x10 0x80000001
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000001
     # Trigger the reset
     mww 0x60008000 0x9c00a000
     # Workaround for stuck in cpu start during calibration.
@@ -64,50 +56,26 @@ proc esp32c3_soc_reset { } {
     sleep 10
     poll
     # Disable the watchdogs again
-    esp32c3_wdt_disable
+    riscv_wdt_disable
 
     # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
     # We will clean allhalted state by resuming the core.
-    riscv dmi_write 0x10 0x40000001
+    riscv dmi_write $_RISCV_DMCONTROL 	0x40000001
 
     # Put the hart back into reset state. Note that we need to keep haltreq set.
-    riscv dmi_write 0x10 0x80000003
+    riscv dmi_write $_RISCV_DMCONTROL 	0x80000003
 }
 
-if { $_RTOS == "none" } {
-    target create $_TARGETNAME riscv -chain-position $_TAPNAME
-} else {
-    target create $_TARGETNAME riscv -chain-position $_TAPNAME -rtos $_RTOS
-}
-
-$_TARGETNAME configure -event reset-assert-post { esp32c3_soc_reset }
-$_TARGETNAME configure -event halted {
-    esp32c3_wdt_disable
-}
-$_TARGETNAME configure -event examine-end {
-    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
-    arm semihosting enable
-    arm semihosting_resexit enable
-    if { [info exists _SEMIHOST_BASEDIR] } {
-        if { $_SEMIHOST_BASEDIR != "" } {
-            # TODO: cherry-pick from upstream
-            # https://review.openocd.org/c/openocd/+/6888
-            # https://review.openocd.org/c/openocd/+/7005
-            # arm semihosting_basedir $_SEMIHOST_BASEDIR
-        }
+proc riscv_memprot_is_enabled { } {
+    # IRAM0 PMS lock, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10A8 0] != 0 } {
+        return 1
     }
+    # DRAM0 PMS lock, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+    if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+        return 1
+    }
+    return 0
 }
-$_TARGETNAME configure -event gdb-attach {
-    halt 1000
-    # by default mask interrupts while stepping
-    riscv set_maskisr steponly
-}
-
-gdb_breakpoint_override hard
 
-riscv set_reset_timeout_sec 2
-riscv set_command_timeout_sec 5
-riscv set_mem_access sysbus progbuf abstract
-riscv set_ebreakm on
-riscv set_ebreaks on
-riscv set_ebreaku on
+create_esp_target $_ESP_ARCH
diff --git a/tcl/target/esp_common.cfg b/tcl/target/esp_common.cfg
index ac8cd6a..af2f6ad 100644
--- a/tcl/target/esp_common.cfg
+++ b/tcl/target/esp_common.cfg
@@ -6,6 +6,14 @@ source [find bitsbytes.tcl]
 source [find memory.tcl]
 source [find mmr_helpers.tcl]
 
+# Riscv Debug Module Registers which are used around esp configuration files.
+set _RISCV_ABS_DATA0	0x04
+set _RISCV_DMCONTROL	0x10
+set _RISCV_ABS_CMD		0x17
+set _RISCV_SB_CS		0x38
+set _RISCV_SB_ADDR0		0x39
+set _RISCV_SB_DATA0		0x3C
+
 # Common ESP chips definitions
 
 # Espressif supports only NuttX in the upstream.
@@ -69,13 +77,12 @@ proc create_esp_target { ARCH } {
 	set_esp_common_variables
 	create_esp_jtag
 	create_openocd_targets
-	configure_openocd_events
+	configure_openocd_events $ARCH
 
 	if { $ARCH == "xtensa"} {
 		configure_esp_xtensa_default_settings
 	} else {
-		# riscv targets are not upstreamed yet.
-		# they can be found at the official Espressif fork.
+		configure_esp_riscv_default_settings
 	}
 }
 
@@ -131,7 +138,6 @@ proc configure_event_halted { } {
 	$_TARGETNAME_0 configure -event halted {
 		global _ESP_WDT_DISABLE
 	    $_ESP_WDT_DISABLE
-	    esp halted_event_handler
 	}
 }
 
@@ -167,12 +173,25 @@ proc configure_event_gdb_attach { } {
 	}
 }
 
-proc configure_openocd_events { } {
+proc configure_openocd_events { ARCH } {
+	if { $ARCH == "riscv" } {
+		configure_event_halted
+	}
 	configure_event_examine_end
 	configure_event_reset_assert_post
 	configure_event_gdb_attach
 }
 
+proc configure_esp_riscv_default_settings { } {
+	gdb_breakpoint_override hard
+	riscv set_reset_timeout_sec 2
+	riscv set_command_timeout_sec 5
+	riscv set_mem_access sysbus progbuf abstract
+	riscv set_ebreakm on
+	riscv set_ebreaks on
+	riscv set_ebreaku on
+}
+
 proc configure_esp_xtensa_default_settings { } {
 	global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME