tcl/target: update esp32c2.cfg to reference shared functions in the esp_common.cfg

This commit enhances code reusability, simplifies maintenance, and ensures
consistency across all chip configurations by consolidating commonly used
commands and variables into the common config file.

Change-Id: I825dd4fddb88e5514429d49ab13869ee6b9a28fc
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>

1 files changed, 68 insertions, 62 deletions

diff --git a/tcl/target/esp32c2.cfg b/tcl/target/esp32c2.cfg
index 2af6dd2..42aeb0a 100644
--- a/tcl/target/esp32c2.cfg
+++ b/tcl/target/esp32c2.cfg
@@ -1,30 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-# The ESP32-C2 only supports JTAG.
-transport select jtag
 
-# Source the ESP common configuration file
+# Source the ESP common configuration file.
 source [find target/esp_common.cfg]
 
-if { [info exists CHIPNAME] } {
-	set _CHIPNAME $CHIPNAME
-} else {
-	set _CHIPNAME esp32c2
-}
-
-if { [info exists CPUTAPID] } {
-	set _CPUTAPID $CPUTAPID
-} else {
-	set _CPUTAPID 0x0000cc25
-}
-
-set _TARGETNAME $_CHIPNAME
-set _CPUNAME cpu
-set _TAPNAME $_CHIPNAME.$_CPUNAME
-
-jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
+# Target specific global variables
+set _CHIPNAME 					"riscv"
+set _CPUTAPID 					0x0000cc25
+set _ESP_ARCH 					"riscv"
+set _ONLYCPU					1
+set _ESP_SMP_TARGET				0
+set _ESP_SMP_BREAK 				0
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60008840
 
-proc esp32c2_wdt_disable { } {
+# Target specific functions should be implemented for each riscv chips.
+proc riscv_wdt_disable { } {
     # Halt event can occur during config phase (before "init" is done).
     # Ignore it since mww commands don't work at that time.
     if { [string compare [command mode] config] == 0 } {
@@ -42,9 +32,9 @@ proc esp32c2_wdt_disable { } {
     mww 0x600080A0 0x84B00000
 }
 
-# This is almost identical with the esp32c3_soc_reset.
-# Will be refactored with the other common settings.
-proc esp32c2_soc_reset { } {
+proc riscv_soc_reset { } {
+	global _RISCV_DMCONTROL
+
     # This procedure does "digital system reset", i.e. resets
     # all the peripherals except for the RTC block.
     # It is called from reset-assert-post target event callback,
@@ -52,7 +42,7 @@ proc esp32c2_soc_reset { } {
     # Since we need the hart to to execute a write to RTC_CNTL_SW_SYS_RST,
     # temporarily take it out of reset. Save the dmcontrol state before
     # doing so.
-    riscv dmi_write 0x10 0x80000001
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000001
     # Trigger the reset
     mww 0x60008000 0x9c00a000
     # Workaround for stuck in cpu start during calibration.
@@ -62,50 +52,66 @@ proc esp32c2_soc_reset { } {
     sleep 10
     poll
     # Disable the watchdogs again
-    esp32c2_wdt_disable
+    riscv_wdt_disable
 
     # Here debugger reads allresumeack and allhalted bits as set (0x330a2)
     # We will clean allhalted state by resuming the core.
-    riscv dmi_write 0x10 0x40000001
+    riscv dmi_write $_RISCV_DMCONTROL 0x40000001
 
     # Put the hart back into reset state. Note that we need to keep haltreq set.
-    riscv dmi_write 0x10 0x80000003
+    riscv dmi_write $_RISCV_DMCONTROL 0x80000003
 }
 
-if { $_RTOS == "none" } {
-    target create $_TARGETNAME riscv -chain-position $_TAPNAME
-} else {
-    target create $_TARGETNAME riscv -chain-position $_TAPNAME -rtos $_RTOS
-}
+proc riscv_memprot_is_enabled { } {
+	global _RISCV_ABS_CMD _RISCV_ABS_DATA0
 
-$_TARGETNAME configure -event reset-assert-post { esp32c2_soc_reset }
-$_TARGETNAME configure -event halted {
-    esp32c2_wdt_disable
-}
-$_TARGETNAME configure -event examine-end {
-    # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
-    arm semihosting enable
-    arm semihosting_resexit enable
-    if { [info exists _SEMIHOST_BASEDIR] } {
-        if { $_SEMIHOST_BASEDIR != "" } {
-            # TODO: cherry-pick from upstream
-            # https://review.openocd.org/c/openocd/+/6888
-            # https://review.openocd.org/c/openocd/+/7005
-            # arm semihosting_basedir $_SEMIHOST_BASEDIR
-        }
-    }
-}
-$_TARGETNAME configure -event gdb-attach {
-    halt 1000
-    # by default mask interrupts while stepping
-    riscv set_maskisr steponly
-}
+	# PMPADDR 0-1 covers entire valid IRAM range and PMPADDR 2-3 covers entire DRAM region
+	# pmpcfg0 holds the configuration for the PMP 0-3 address registers
+
+	# read pmpcfg0 and extract into 8-bit variables.
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203a0
+	set pmpcfg0 [riscv dmi_read $_RISCV_ABS_DATA0]
+
+	set pmp0cfg [expr {($pmpcfg0 >> (8 * 0)) & 0xFF}]
+	set pmp1cfg [expr {($pmpcfg0 >> (8 * 1)) & 0xFF}]
+	set pmp2cfg [expr {($pmpcfg0 >> (8 * 2)) & 0xFF}]
+	set pmp3cfg [expr {($pmpcfg0 >> (8 * 3)) & 0xFF}]
+
+	# read PMPADDR 0-3
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b0
+	set pmpaddr0 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b1
+	set pmpaddr1 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b2
+	set pmpaddr2 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+	riscv dmi_write $_RISCV_ABS_CMD 0x2203b3
+	set pmpaddr3 [expr {[riscv dmi_read $_RISCV_ABS_DATA0] << 2}]
+
+	set IRAM_LOW 	0x40380000
+	set IRAM_HIGH 	0x403C0000
+	set DRAM_LOW 	0x3FCA0000
+	set DRAM_HIGH 	0x3FCE0000
+	set PMP_RWX     0x07
+	set PMP_RW     	0x03
 
-gdb_breakpoint_override hard
+	# The lock bit remains unset during the execution of the 2nd stage bootloader.
+	# Thus we do not perform a lock bit check for IRAM and DRAM regions.
+
+	# Check OpenOCD can write and execute from IRAM.
+	if {$pmpaddr0 >= $IRAM_LOW && $pmpaddr1 <= $IRAM_HIGH} {
+    	if {($pmp0cfg & $PMP_RWX) != 0 || ($pmp1cfg & $PMP_RWX) != $PMP_RWX} {
+			return 1
+		}
+	}
+
+	# Check OpenOCD can read/write entire DRAM region.
+	if {$pmpaddr2 >= $DRAM_LOW && $pmpaddr3 <= $DRAM_HIGH} {
+    	if {($pmp2cfg & $PMP_RW) != 0 && ($pmp3cfg & $PMP_RW) != $PMP_RW} {
+			return 1
+		}
+	}
+
+	return 0
+}
 
-riscv set_reset_timeout_sec 2
-riscv set_command_timeout_sec 5
-riscv set_mem_access sysbus progbuf abstract
-riscv set_ebreakm on
-riscv set_ebreaks on
-riscv set_ebreaku on
+create_esp_target $_ESP_ARCH