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| author | Marek Vrbka <marek.vrbka@codasip.com> | 2023-08-21 13:49:43 +0200 |
|---|---|---|
| committer | Marek Vrbka <marek.vrbka@codasip.com> | 2023-08-25 07:54:59 +0200 |
| commit | 0b914fe5ae5f29e5676755286068861dece5ebeb (patch) | |
| tree | 435f2b4d8879a9704e4b1d8feb364eae49a050a6 | |
| parent | 5cb60e3f7d1b2eca5e376a6a829bdd3659c35f54 (diff) | |
| download | riscv-openocd-0b914fe5ae5f29e5676755286068861dece5ebeb.zip riscv-openocd-0b914fe5ae5f29e5676755286068861dece5ebeb.tar.gz riscv-openocd-0b914fe5ae5f29e5676755286068861dece5ebeb.tar.bz2 | |
target/riscv: Don't write to zero.
During a previous patch, the ignoring of writes to register zero
was deleted. This patch restores it to the original.
Change-Id: Ieb028a5b2e3f691e4847713c7bc809e10726e18c
Signed-off-by: Marek Vrbka <marek.vrbka@codasip.com>
| -rw-r--r-- | src/target/riscv/riscv.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index c404b14..01517cf 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -4718,6 +4718,9 @@ unsigned int riscv_count_harts(struct target *target) */ static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write) { + if (regno == GDB_REGNO_ZERO) + return !is_write; + /* GPRs, FPRs, vector registers are just normal data stores. */ if (regno <= GDB_REGNO_XPR31 || (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) || |