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| author | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-03 16:42:14 +0300 |
|---|---|---|
| committer | Evgeniy Naydanov <evgeniy.naydanov@syntacore.com> | 2024-04-05 14:19:33 +0300 |
| commit | 9c45c9f4bed24c54ac736b15399f889b25e68fe6 (patch) | |
| tree | 941224cf6fca8b902ba4a70c05ed446704f26204 | |
| parent | 722cef1ae0ec55ee7aa47e60acafaa787be16b32 (diff) | |
| download | riscv-openocd-9c45c9f4bed24c54ac736b15399f889b25e68fe6.zip riscv-openocd-9c45c9f4bed24c54ac736b15399f889b25e68fe6.tar.gz riscv-openocd-9c45c9f4bed24c54ac736b15399f889b25e68fe6.tar.bz2 | |
target/riscv: read registers are not valid on a running target
Change-Id: I2c5335bb6055b767d3c3ffb3f6910b71b9c2bb35
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
| -rw-r--r-- | src/target/riscv/riscv.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 60c26ba..5b994ee 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -5260,7 +5260,8 @@ int riscv_get_register(struct target *target, riscv_reg_t *value, return ERROR_FAIL; buf_set_u64(reg->value, 0, reg->size, *value); - reg->valid = gdb_regno_cacheable(regid, /* is write? */ false); + reg->valid = gdb_regno_cacheable(regid, /* is write? */ false) && + target->state == TARGET_HALTED; reg->dirty = false; LOG_TARGET_DEBUG(target, "Read %s: 0x%" PRIx64, reg->name, *value); |