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| author | Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com> | 2019-11-28 00:24:25 +0100 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2019-11-27 15:24:25 -0800 |
| commit | e03dd199e05923abda2dbc86ebc97d92531ef294 (patch) | |
| tree | adaa85889788ffd76ccd40221b1b49000d95c306 | |
| parent | de00906ebd6edc74c0cf5fff0d3d7beb82c39b7b (diff) | |
| download | riscv-openocd-e03dd199e05923abda2dbc86ebc97d92531ef294.zip riscv-openocd-e03dd199e05923abda2dbc86ebc97d92531ef294.tar.gz riscv-openocd-e03dd199e05923abda2dbc86ebc97d92531ef294.tar.bz2 | |
Fixed write_memory_progbuf() on RV64. (#426)
Abstract write size (aarsize) to shall always match the real
size of the register. This is because abstract write of smaller size
than the register need not be supported per spec (pg. 13 of RISC-V
External Debug Support ver. 0.13.2).
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 417cb9f..548c6d5 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -3232,7 +3232,7 @@ static int write_memory_progbuf(struct target *target, target_addr_t address, /* Write and execute command that moves value into S1 and * executes program buffer. */ uint32_t command = access_register_command(target, - GDB_REGNO_S1, size > 4 ? 64 : 32, + GDB_REGNO_S1, riscv_xlen(target), AC_ACCESS_REGISTER_POSTEXEC | AC_ACCESS_REGISTER_TRANSFER | AC_ACCESS_REGISTER_WRITE); |