diff options
| author | Tim Newsome <tim@sifive.com> | 2020-04-20 15:22:01 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2020-04-20 15:22:01 -0700 |
| commit | bd7d75d4b936dcefc24ea8fb1314876bb5bd6953 (patch) | |
| tree | 4b3300bd2a60e7362801319bc9a1c466617963ae | |
| parent | eaabf76fde861185f3b1eac564b2881a493aa45d (diff) | |
| download | riscv-openocd-bd7d75d4b936dcefc24ea8fb1314876bb5bd6953.zip riscv-openocd-bd7d75d4b936dcefc24ea8fb1314876bb5bd6953.tar.gz riscv-openocd-bd7d75d4b936dcefc24ea8fb1314876bb5bd6953.tar.bz2 | |
Fix whitespace.
Change-Id: I05c5342d8a461cd8c618a3f60296925e9e84643f
| -rw-r--r-- | src/target/riscv/riscv.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index f4836e9..2d04e9f 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -3001,7 +3001,7 @@ bool riscv_has_register(struct target *target, int hartid, int regid) return 1; } -/** +/** * If write is true: * return true iff we are guaranteed that the register will contain exactly * the value we just wrote when it's read. @@ -3035,7 +3035,7 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write) case GDB_REGNO_MEPC: case GDB_REGNO_MCAUSE: case GDB_REGNO_SATP: - /* + /* * WARL registers might not contain the value we just wrote, but * these ones won't spontaneously change their value either. * */ |