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| author | Megan Wachs <megan@sifive.com> | 2017-05-22 22:02:01 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-05-22 22:02:01 -0700 |
| commit | e12f5575ef408fc83b66851b8c2ed05503509a49 (patch) | |
| tree | 8984b529d7e9865f25430c9b3e45c97af3040737 | |
| parent | c431c0eb251bf6d02959a6f55be3baba04552b5d (diff) | |
| download | riscv-openocd-e12f5575ef408fc83b66851b8c2ed05503509a49.zip riscv-openocd-e12f5575ef408fc83b66851b8c2ed05503509a49.tar.gz riscv-openocd-e12f5575ef408fc83b66851b8c2ed05503509a49.tar.bz2 | |
riscv-v11: Don't perform unexpected operation in cache_write
| -rw-r--r-- | src/target/riscv/riscv-011.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 8663082..6ed3ba1 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -872,7 +872,7 @@ static int cache_write(struct target *target, unsigned int address, bool run) if (last == info->dramsize) { // Nothing needs to be written to RAM. - dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT); + dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | (run ? DMCONTROL_INTERRUPT : 0)); } else { for (unsigned int i = 0; i < info->dramsize; i++) { |