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| author | Jan Čapek <jan.capek@braiins.cz> | 2017-01-25 10:11:48 +0100 |
|---|---|---|
| committer | Freddie Chopin <freddie.chopin@gmail.com> | 2017-04-24 21:57:57 +0100 |
| commit | b375052c58a4ef9b855ce9aa119cc1abf432d0c8 (patch) | |
| tree | d8e74f7a48b9cc7872d3ac2acdc19589cc35f1c2 | |
| parent | e916bcda6435a60acaec30ce2edf9f3341c01c67 (diff) | |
| download | riscv-openocd-b375052c58a4ef9b855ce9aa119cc1abf432d0c8.zip riscv-openocd-b375052c58a4ef9b855ce9aa119cc1abf432d0c8.tar.gz riscv-openocd-b375052c58a4ef9b855ce9aa119cc1abf432d0c8.tar.bz2 | |
tcl STM32L0xx - add support for dual banked targets and for Nucleo-64 STM32L073
- stm32l0_dual_bank.cfg - implement dual bank configuration
- st_nucleo_l073rz.cfg - implement new board script
Change-Id: Ie8063e5bec45069a63d414d81b2068fe3cc7e4d7
Signed-off-by: Jan Čapek <jan.capek@braiins.cz>
Reviewed-on: http://openocd.zylin.com/3957
Reviewed-by: Cezary Gapiński <cezary.gapinski@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Tested-by: jenkins
Reviewed-by: Aurelio Lucchesi <me@0rel.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
| -rw-r--r-- | tcl/board/st_nucleo_l073rz.cfg | 12 | ||||
| -rw-r--r-- | tcl/target/stm32l0_dual_bank.cfg | 5 |
2 files changed, 17 insertions, 0 deletions
diff --git a/tcl/board/st_nucleo_l073rz.cfg b/tcl/board/st_nucleo_l073rz.cfg new file mode 100644 index 0000000..fa9dc87 --- /dev/null +++ b/tcl/board/st_nucleo_l073rz.cfg @@ -0,0 +1,12 @@ +# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip. +# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +set WORKAREASIZE 0x2000 + +source [find target/stm32l0_dual_bank.cfg] + +# There is only system reset line and JTAG/SWD command can be issued when SRST +reset_config srst_only diff --git a/tcl/target/stm32l0_dual_bank.cfg b/tcl/target/stm32l0_dual_bank.cfg new file mode 100644 index 0000000..f9f1a4e --- /dev/null +++ b/tcl/target/stm32l0_dual_bank.cfg @@ -0,0 +1,5 @@ +source [find target/stm32l0.cfg] + +# Add the second flash bank. +set _FLASHNAME $_CHIPNAME.flash1 +flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME |